This paper presents two computer architecture mechanisms that can be employed together to allow programs to be written where their individual instructions can (1) be executed in parallel in separate processors and (2) be arbitrarily assigned to be executed by any processor in a connected fabric of processors. This is an emerging parallel execution technique for future high performance and embedded computers. Changing the placement of a program's instructions in a processing fabric is equivalent to rearranging the computer architecture around the program itself. Reasons to change the computer architecture around the software are to improve overall execution speed and to perform load balancing. The two computer architecture mechanisms are (1) a custom dataflow instruction set and (2) a processor block called an operation cell. The most important feature of the instruction set is the high level of operational independence of the instructions (i.e. no shared memory/registers between instructions). The operation cell is a processor construct that stores an instruction and manages the execution life of that instruction. An operation cell either executes the instruction itself or forwards the execution to another operation cell in a different processor.

A dataflow processor is presented that is to be used as the basis of a tiled polymorphic computing architecture. The key contribution is a new scheme that allows a program's instructions to be migrated before and during runtime in a fine-grained manner across the collection of processors. The primary reason to perform this migration is to execute programs faster. Other reasons to perform instruction migration are to prioritize computational resources and to achieve thermal balancing. The act of performing instruction migration across of a collection of processors is logically equivalent to rearranging the computer architecture under the program (i.e., polymorphic computing). Additionally, a new dataflow instruction set which enables the migration is presented. This instruction set is built upon the concept of a single RISC-like dataflow instruction that can atomically execute, make decisions, and independently route results. Furthermore, the novel concept of an operation cell is presented. An operation cell holds a single instruction and its data. It also contains logic to independently determine when an instruction is executed and when to forward data to other operation cells in the collection of processors. In addition, the internal architecture of this processor is presented. This includes the arithmetic logic unit (ALU) that is used to execute the instructions and a series of buses that allow data movement to occur in parallel to instruction execution. Finally, an inter-processor migration strategy is defined.