In this work, both analogue and digital depletion-mode single channel transistor circuits are presented and are simulated using an n-channel IGZO technology with$\boldsymbol{V}_{\boldsymbol{TH}}= -\mathrm{0}.\mathbf{87}\mathbf{V}$. A logic family is introduced, suppressing the need for an additional voltage level and level restoring circuitry. Furthermore, in the analogue domain, a depletion current mirror topology is presented with demonstrated small current error. Finally, the current mirror is used in the design of an OpAmp, achieving a simulated open-loop gain of 45 dB, CMRR of 58 dB, unity-gain frequency of 444 kHz and a phase margin of 71 degrees.

This paper reports on recent activities by the Portugal Chapter of IEEE Education Society. It begins with a reflection on the work of a Chapter and on several aspects that may impact its performance. The major activities are also presented, as well as the policies developed by the Portugal Chapter in the last year, concluding with the presentation of the two awards received at the last FIE, namely the Chapter Achievement Award and the Distinguished Chapter Leadership Award.

A multifunctional router IC to be included in the nodes of a wearable body sensor network is described and evaluated. The router targets different application scenarios, especially those including tens of sensors, embedded into textile materials and with high data-rate communication demands. The router IC supports two different functionality sets, one for sensor nodes and another for the base node, both based on the same circuit module. The nodes are connected to each other by means of woven thick conductive yarns forming a mesh topology with the base node at the center. From the standpoint of the network, each sensor node is a four port router capable of handling packets from destination nodes to the base node, with sufficient redundant paths. The adopted hybrid circuit and packet switching scheme significantly improve network performance in terms of end-to-end delay, throughput and power consumption. The IC also implements a highly precise, sub-microsecond one-way time synchronization protocol which is used for time stamping the acquired data. The communication module was implemented in a 4-metal,$0.35~\mu \text{m}$CMOS technology. The maximum data rate of the system is 35 Mbps while supporting up to 250 sensors, which exceeds current BAN applications scenarios.

Security is now becoming a well-established challenge for integrated circuits (ICs). Various types of IC attacks have been reported, including reverse engineering IPs, dumping on-chip data, and controlling/modifying IC operation. IEEE 1149.1, commonly known as Joint Test Action Group (JTAG), is a standard for providing test access to an IC. JTAG is primarily used for IC manufacturing test, but also for in-field debugging and failure analysis since it gives access to internal subsystems of the IC. Because the JTAG needs to be left intact and operational after fabrication, it inevitably provides a “backdoor” that can be exploited outside its intended use. This paper proposes machine learning-based approaches to detect illegitimate use of the JTAG. Specifically, JTAG operation is characterized using various features that are then classified as either legitimate or attack. Experiments using the OpenSPARC T2 platform demonstrate that the proposed approaches can classify legitimate JTAG operation and known attacks with significantly high accuracy. Experiments also demonstrate that unknown and disguised attacks can be detected with high accuracy as well (99% and 94%, respectively).

IEEE 1687 standard (IJTAG), as an extension to the IEEE 1149.1, facilitates efficient access to embedded instruments by supporting reconfigurable scan networks. Specifically, IJTAG allows each IP to be wrapped by a test data register (TDR) whose access is controlled by a segment insertion bit (SIB) or a scan-mux control bit (SCB). Because the TDRs and the SIB/SCB network are typically not public, but critical for accessing embedded instruments, they might be used for illegitimate purposes, such as dumping credential data and reverse engineering IP design. Machine learning has been proposed to detect such attacks, but the large number of instruments and parallel execution enabled by the IJTAG produce high-dimensional data, which poses a challenge to on-chip detection. In this paper, we propose to reduce the high-dimensional but sparse data using a low-density parity-check (LDPC) matrix. Experiments using a modified version of the OpenSPARC T2 to include IJTAG functionality demonstrate that the use of feature reduction eliminates 91% of the features, leading to 43% reduction in circuit size without affecting detection accuracy. Also, the on-chip detector adds moderate overhead (~ 8%) to the IJTAG.

A novel linear analog adder is proposed only with n-type enhancement IGZO TFTs that computes summation of four voltage signals. However, this design can be easily extended to perform summation of higher number of signals, just by adding a single TFT for each additional signal in the input block. The circuit needs few number of transistors, only a single power supply irrespective of the number of voltage signals to be added, and offers good accuracy over a reasonable range of input values. The circuit was fabricated on glass substrate with the annealing temperature not exceeding 200° C. The circuit performance is characterized from measurements under normal ambient at room temperature, with a power supply voltage of 12 V and a load of ≈ 4 pF. The designed circuit has shown a linearity error of 2.3% (until input signal peak to peak value is 2 V), a power consumption of 78 μW and a bandwidth of ≈ 115 kHz, under the worst case condition (when it is adding four signals with the same frequency). In this test setup, it has been noticed that the second harmonic is 32 dB below the fundamental frequency component. This circuit could offer an economic alternative to the conventional approaches, being an important contribution to increase the functionality of large area flexible electronics.

This paper presents a wide input range, low-power operational transconductance amplifier (OTA) in weak inversion. The OTA is implemented with tanh-triplets differential pairs, degenerated by a composite configuration to augment the input linear range, thus reducing further the harmonic distortion. Using MATLAB, the mismatch factor (A) of a typical multi-tanh triplet has been optimised for minimum harmonic distortion. The OTA is designed in UMC 0.13um CMOS technology with 1.2V supply. Simulations show that the input range can be extended to 300 mV, while keeping the HD3 below −80 dB. The average power consumption is 13nW, with an open loop-gain of 76 dB and a unity gain frequency of 250 Hz. The low harmonic distortion OTA can find potential applications in low-power and long time constant filters.

This paper describes and evaluates a fully digital circuit for one-way master-to-slave highly precise time synchronization in a low-power, wearable system equipped with a set of sensor nodes connected in a mesh network. Sensors are connected to each other with conductive yarns that are used as one-wire bidirectional communication links. The circuit is designed to perform synchronization in the Medium Access Control (MAC) layer. In each sensor node, the synchronization circuit provides a synchronized, programmable clock signal and a real-time counter for time stamping. Experimental results obtained with an implementation in 0.35 μm CMOS technology for a network of electromyography sensors show that the circuit keeps the one-hop average clock skew below 4.6 ns, a value small enough to satisfy many wearable application requirements.

Sparse coding techniques have seen an increasing range of applications in recent years, especially in the area of image processing. In particular, sparse coding using ℓ1-regularization has been efficiently solved with the Augmented Lagrangian (AL) applied to its dual formulation (DALM). This paper proposes the decomposition of the dictionary matrix in its Singular Value/Vector form in order to simplify and speed-up the implementation of the DALM algorithm. Furthermore, we propose an update rule for the penalty parameter used in AL methods that improves the convergence rate. The SVD of the dictionary matrix is done as a pre-processing step prior to the sparse coding, and thus the method is better suited for applications where the same dictionary is reused for several sparse recovery steps, such as block image processing.

This paper presents a network circuit for wearable low-power BAN (Body Area Networks) applications, geared towards mesh network topologies with conductive yarns as transmission channels. The design and implementation of the physical and MAC layers is described. The resulting circuit sends and receives data simultaneously, and experimental results indicate that the proposed system works with variable data rates, up to a maximum of 9+9 Mbps. All reported measurements were collected from working FPGA-based prototypes, and the performance achieved shows that the circuit is suitable for use in reliable high-speed low-power BAN applications.

This paper presents two initiatives run by groups of engineering students at the University of Porto: the Microelectronics Students' Group and BioStar. These groups are student-led initiatives that promote different scientific fields through self-guided projects. Both experiences have proven to be very successful in increasing the undergraduate student's interest in science and technology. This work reports the activities, organization and main methodologies employed by these groups, which can be seen as successful approaches to enhance the technical curriculum of students.

This work addresses a built-in self-test methodology for circuit cell identification under specific matching conditions. The proposed technique is applied to the CMOS realization of a reduced-KII network, which is a system model of the biological olfactory cortex. This model behaves as an associative memory, a useful tool for information and adaptive processes. Based on a mixed-signal approach, the test strategy makes proper use of the circuits comprising the network structure, and provides self reconfiguration as well. Both testing procedures and design of essential building blocks are described in this paper. Simulation results are presented for a reduced-KII network comprising 128-cells, sequentially tested for matching in terms of offsets and their dynamic performances.

This paper reviews the problem of translating signals into symbols preserving maximally the information contained in the signal time structure. In this context, we motivate the use of nonconvergent dynamics for the signal to symbol translator. We then describe a biologically realistic model of the olfactory system proposed by W. Freeman (1975) that has locally stable dynamics but is globally chaotic. We show how we can discretize Freeman's model using digital signal processing techniques, providing an alternative to the more conventional Runge-Kutta integration. This analysis leads to a direct mixed-signal (analog amplitude/discrete time) implementation of the dynamical building block that simplifies the implementation of the interconnect. We present results of simulations and measurements obtained from a fabricated analog VLSI chip.

This paper presents a low power MOS-VLSI implementation of an oscillator proposed by Freeman (1975) to model a very important component of the olfactory cortex. The model dynamics has time constants in the order of 1/220 (s). To accomplish the long time constants a new filtering technique recently proposed was utilized. All the blocks involving information processing were designed to operate below threshold (weak inversion).