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Maysam Lavasani

dblp:75/10926 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 33% Electronic design automation · 33% Hardware accelerators and domain-specific architectures · 33%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
data-parallel acceleration
0.112012
Compiling high throughput network processors · FPGA 2012
Reconfigurable computing and FPGAs
FPGA compilation
0.112012
Compiling high throughput network processors · FPGA 2012
Electronic design automation
high-level synthesis
0.112012
Compiling high throughput network processors · FPGA 2012

Methods — techniques the papers use, named apart from their topics

stylized c compilation · 0.1FPGA-tailored parallelization · 0.1
YearPublicationVenuePosition
2013 An FPGA-based in-line accelerator for Memcached
Maysam Lavasani, Hari Angepat, Derek Chiou
Hot Chips Symposium1
2012 Compiling high throughput network processors
abstract
Gorilla is a methodology for generating FPGA-based solutions especially well suited for data parallel applications with fine grain irregularity. Irregularity simultaneously destroys performance and increases power consumption on many data parallel processors such as General Purpose Graphical Processor Units (GPGPUs). Gorilla achieves high performance and low power through the use of FPGA-tailored parallelization techniques and application-specific hardwired accelerators, processing engines, and communication mechanisms. Automatic compilation from a stylized C language and templates that define the hardware structure coupled with the intrinsic flexibility of FPGAs provide high performance, low power, and programmability.
Maysam Lavasani, Larry Dennison, Derek Chiou
FPGA1