Novel approaches for the development of integrated molecular analysis tools have been tested. A label-free method for molecular detection and characterization based on UV absorbance has been applied and two technologies of silicon photodetectors arrays have been selected to fulfil the requirements of the different applications

The paper describes the design of a smart sensor for label-free detection of DNA hybridization. The sensor is based on a direct electrical transduction principle: it measures impedance variation at the interface between a bio-functionalized electrode and a solution containing the analyte. The smart sensor includes a complete signal conditioning and processing subsystem based on an embedded /spl mu/-controller. We outline the sensor architecture, and we describe in detail board-level integration as well as hardware and software implementation and design choices. The accuracy of our embedded solution has been evaluated by comparing it with a high-cost laboratory setup. Moreover, we provide measurements of real sensing structures which demonstrate the functionality of our system in the field.

Motion capture is an emerging technology enabling the design of natural user interfaces for wearable devices based on gestural recognition. However, costs and energy requirements are critical factors to enable their diffusion to low-end wearable systems. Current commercial products do not match these requirements. For this reason, we developed a low-cost/low-power wearable motion tracking system, based on integrated accelerometers, called MOCA (motion capture with accelerometers). Our system is composed of sensing units connected to a control/acquisition board, responsible for reading and preprocessing data, and a mobile terminal running the recognition algorithm. Experiments performed to validate accuracy, power consumption and real-time performance demonstrate low-power and flexibility features of the proposed tracking system as well as its effectiveness as an input interface.

The use of simple digital window comparators for the on-chip evaluation of analogue signals is described. It is shown that a window can be created by choosing different gate input configurations. The potential problem of lot-to-lot variation of the comparator window position can be compensated by an on-chip repositioning technique. The components for the implementation comprise of a reference comparator and the evaluation comparators that are described along with the implementation of the technique. It is shown, that this technique allows the automatic lot condition adjustment for the evaluation comparator windows. The technique can optionally provide lot condition diagnostics for the test record as well as diagnosis of the actual window selection of the evaluation comparator.

This paper presents a synthetic overview of multilevel (ML) flash memory program methods. The problem of increasing program time with the number of bits stored in each cell is discussed and methods based on both channel hot electrons (CHE) and Fowler-Nordheim tunneling (FNT) are discussed. In the case of CHE, the use of an increasing voltage rather than a constant one on the control gate (CG) leads to narrower threshold voltage distributions and smaller current absorption, with positive effects on the degree of parallelism and program throughput. As for FNT, much faster programming than that commonly used today can be done using high CG voltages without producing intolerable degradation of cell reliability.

Many portable devices, like laptops and PDAs can be powered by different combinations of two or more battery packs to give the user the possibility to choose an optimal compromise between lifetime and weight/size. The common discharge policy for multiple battery packs is sequential, i.e., the system switches to the second pack when the first one is empty. In this work we demonstrate that this policy is not optimal by proving the effectiveness of two other policies, namely switched and series, which significantly extend battery lifetime, but require some additional control circuitry. We present a complete implementation of the power supply circuitry and detailed measurements on battery discharge times. Significant lifetime extensions (20 to 30 %) have been achieved for dual-battery systems under high current load.

Display power consumption is often the most significant contributor to the overall power budget for many portable devices. Traditionally, liquid crystal display (LCD) power minimization has focused on technology and circuit design. In this paper we take an orthogonal approach, and we introduce several software-only techniques for LCD dynamic power management, which do not require any hardware changes on existing LCDs and their controllers. The power savings achieved are significant: from 40% (with no perceivable image degradation) to 60% (with significant, but tolerable degradation) of total system power, measured on a prototype wearable system platform.

We propose a self-checking scheme for the on-line testing of power supply noise, exceeding a tolerance bound, to be chosen according to system constraints. Upon the occurrence of such a noise, our scheme provides an output error message, which can be exploited for diagnostic purposes or to recover from the detected noise (thus guaranteeing correct system operation). As far as we are aware, no on-line testing scheme for power supply noise has been proposed up to now. Our scheme has negligible impact upon system performance, features a self-checking ability (with respect to a wide set of possible internal faults) and reveals, on-line, the occurrence of power supply noise, despite the possible presence of noise affecting ground.

In advanced robotic applications where a physical interaction of the robot with the environment takes place, the measurement of interaction forces is of basic importance for a safe execution of the desired tasks. In the paper, a 'stress' sensor is presented and its basic characteristics illustrated and discussed. Among its positive features, one may find the very compact size, good electrical properties, and the fact that it can be easily 'constructed' directly on the mechanical part by deposition of the sensing elements directly on the mechanical structure. These are very interesting properties for its use in advanced robotic systems.

The impact of global on-chip interconnections on power consumption and speed of integrated circuits is becoming a serious concern. Designers need therefore to quickly estimate how performance and power are affected by a given choice of the interconnection parameters (length, voltage swing, driver and receiver schematics and sizing). This work focuses on the entire communication channel (driver, interconnect, receiver), and provides high level parametric VHDL simulation models for low-swing signaling schemes. These SPICE-derived power and timing macromodels transfer electrical-level information to the RTL simulation in an event-driven fashion, as transitions occur at the input of the interconnect driver. The accuracy reached by this back-annotation technique is within 5% with respect to SPICE results, with only 4% simulation speed penalty in the worst case.

A significant fraction of the power in portable devices (handheld terminals, PDAs, laptops, etc.) is drawn by the wireless network interface card (NIC). We test the viability of a novel power management technique, based on the exploitation of the NIC off-mode while a client-controlled streaming multimedia application is in progress. The basic idea is to switch off the card while frames are being played back, until a low-threshold level is reached in the client buffer. In this paper, pessimistic assumptions are made on the timing and power overheads associated with recovering the card from off-mode, but nevertheless a power saving of about 25% is achieved over the average power consumption incurred by the standard IEEE 802.11 mechanism. We also provide design curves showing the minimum buffer size that makes our technique effective, as a function of the network bandwidth and of the card characteristics.

This paper addresses the problem of power consumption in multimedia system architectures and presents an algorithmic optimization technique to achieve the goal of power reduction in the context of real time processing. The technique is based on a mixed speed-setting and shutdown policy. We address the problem from both a theoretical and practical point of view, by presenting a power efficient implementation of a MPEG-layer3 real-time decoder algorithm designed for wearable devices as a case study. The target system is the Hewlett-Packard's SmartBadgeIII prototype of wearable system based on the StrongARM1100 processor. Theoretical analysis as well as quantitative results of power measurements are provided to show the effectiveness of this technique. The experimental set-up is also described.

In this paper we propose a self-checking scheme for the on-line testing of transient and crosstalk faults affecting the interconnections of synchronous systems implemented using Field-Programmable Gate-Arrays (FPGAs). An FPGA prototype has been implemented, whose correct operation has been verified by means of post-layout simulations and experimental measurements.

In this paper, we describe a software-controlled approach for adaptively minimizing energy in embedded systems for real-time multimedia processing. Energy is optimized by clock speed setting: the software controller dynamically adjusts processor clock speed to the frame rate (FR) requirements of the incoming multimedia stream. The speed-setting policy is based on a system model that correlates clock speed with best case, average case, and worst case sustainable FRs, accounting for data dependency in multimedia streams. The technique has been implemented in a energy-efficient MPEG3 real-time decoder algorithm designed for wearable devices as a case study. The target system is the Hewlett-Packard SmartBadgeIII prototype system based on the StrongARM1100 processor. Hardware measurements show that computational energy can be drastically reduced (up to 40%) with respect to fixed-frequency operation.

Summary form only given. This paper presents a self-checking, on-line testing and diagnosis scheme for bus lines affected by intermediate voltage values possibly due to bridging faults, or to different kinds of faults affecting the bus connected units.

We present a self-checking detection and diagnosis scheme for transient, delay, and crosstalk faults affecting bus lines of synchronous systems. Faults that are likely to result in the connected logic sampling incorrect bus data are on-line detected. The position of the affected line(s) within the considered bus is identified and properly encoded. The proposed scheme is self-checking with respect to a realistic set of possible internal faults, including node stuck-ats, transistor stuck-ons, transistor stuck-opens, resistive bridgings, transient faults, delays and crosstalks.

In this work we propose an exact technique for efficient computation of signal statistics during high-level synthesis for low-power of general control-dominated designs. Our approach does not require iterative simulation: simulation is performed once for all to collect boundary information that will be repeatedly exploited for computing signal statistics for alternative implementations.

This paper presents a digital scheme to correct undesired skews between couples of clocks of synchronous systems. Correction is automatically and very fastly performed during system run-time. The proposed scheme is self-checking with respect to a wide set of possible internal (permanent as well as temporary) faults, and is easily scalable to account for different skew tolerance/sensitivity requirements. It is suitable to be implemented in VLSI, very deep submicron technology, as well as using field programmable gate arrays.

This paper presents a novel 1-out-of-n checker that, compared to the other implementations up to now presented, features the advantages of: (i) satisfying the TSC or SCD property with respect to all possible internal faults representative of realistic failures; (ii) presenting a single output line; (iii) requiring significantly lower area overhead.

Most work to date on power reduction has focused at the component level, not at the system level. In this paper, we propose a framework for describing the power behavior of system-level designs. The model consists of a set of resources, an environmental workload specification, and a power management policy, which serves as the heart of the system model. We map this model to a simulation-based framework to obtain an estimate of the system's power dissipation. Accompanying this, we propose an algorithm to optimize power management policies. The optimization algorithm can be used in a tight loop with the estimation engine to derive new power-management policy algorithms for a given system-level description. We tested our approach by applying it to a real-life low-power portable design, achieving a power estimation accuracy of ∼10%, and a 23% reduction in power after policy optimization.

This paper analyses the problem of systems' on-line testing with respect to logic errors due to crosstalk, delay and transient faults. In particular we show that logic errors due to crosstalk noise between internal, adjacent lines may not be on-line detectable by conventional concurrent error detection techniques using error detecting codes. Hence, a detector is proposed that allows the on-line detection of such logic errors, and that is self-checking with respect to a wide set of possible internal faults representative of realistic failures, including crosstalk, delay, and transient faults.

When thinking of semiconductor memories, it comes naturally to associate stored bits and memory cells with a one-to-one relationship. That, however, is not really a must nor necessarily the most convenient solution for data storage, since using analog signals and digital-to-analog (D/A) as well as analog-to digital (A/D) conversions a large number of bits could be memorized in a single cell, although, of course, the use of analog signals presents all drawbacks of signal-to-noise ratio that are so well known in electronics. In fact, the real question in this sense concerns the number of bits used for the A/D and D/A conversions, since the conventional (fully) digital case can be seen as the simplest realization of a general approach tending to infinitely precise analog storage (i.e. an infinite number of stored bits per cell) at the other extreme. Naturally, in the real world the conflicting aspects of density (measured in bits per cell) and noise immunity (in a general sense) should be traded off one against the other looking for optimum use of silicon area, of course depending on technology, architectures, circuits and reliability. From this point of view it is obvious that the fully digital approach based on the one-bit one-cell concept does not represent necessarily the best solution. Recently, this general question has assumed real and practical significance for nonvolatile memories, since devices storing two bits per cell are now being introduced on the market. At the same time, in a number of research labs a significant effort is currently being dedicated to the study of the limits and practical convenience of storage density considering the current state of the art in technology and circuit designs. This problem, however, presents a number of interacting aspects concerning cell concept, programming and reading schemes, and architectures and reliability that are of interest well beyond the field of nonvolatile memories, because they are ultimately dealing with the basic question of analog versus digital signals. In this contrast, the present paper considers the question of multilevel nonvolatile memories in all its interacting aspects, analyzing both the current state of the art and the future possibilities.

This paper proposes an on-line testing scheme for permanent and temporary faults which affect signals of the clock distribution network of synchronous systems, and which make them stuck-at, or change with incorrect frequency or duty-cycle. By means of straightforward modifications, the proposed scheme can be also used to detect on-line undesired skews between couples of clock signals.

In this paper a single output self-checking n-input comparator is presented. The proposed circuit, which can be used as n-variable two-rail checker or as equality checker features a compact structure, is Totally-Self-Checking or Strongly Code-Disjoint with respect to a wide set of realistic faults, and requires a limited set of input code words for fault detection (thus it can be used to implement also embedded comparators).

This paper investigates the detection of parametric bridging and delay faults affecting the functional block of CMOS self-checking circuits (SCCs). As far as these faults are concerned, classical definitions are shown to become ambiguous because they are entirely based on logic considerations. Thus, new definitions are proposed here to consider the analog and dynamic effects of such faults, and to ensure that they do not produce any problem at the system level. Moreover, electrical level design rules aimed at satisfying these conditions are proposed for self-checking circuits with combinational functional blocks. The problem of their practicability and effectiveness is analyzed in detail, and is shown by means of significant examples.

In this paper, we present a new gate-level approach to power and current simulation. We propose a symbolic model of complementary metal-oxide-semiconductor (CMOS) gates to capture the dependence of power consumption and current flows on input patterns and fan-in/fan-out conditions. Library elements are characterized and their models are used during event-driven logic simulation to provide power information and construct time-domain current waveforms. We provide both global and local pattern-dependent estimates of power consumption and current peaks (with accuracy of 6 and 10% from SPICE, respectively), while keeping performance comparable with traditional gate-level simulation with unit delay. We use VERILOG-XL as simulation engine to grant compatibility with design tools based on Verilog HDL. A Web-based user interface allows our simulator (PPP) to be accessed through the Internet using a standard web browser.

PPP is a Web-based simulation and synthesis environment for low-power design.In this paper we describe the gate-level simulation engine of PPP, that achieves accuracy always within 6% from SPICE, while keeping performance c ompetitive with traditional gate-level simulation.This is done by using advanced symbolic models of the basic library cells, that exploit the physical understanding of the main powerconsuming phenomena.VERILOG-XL is used as simulation platform to maintain compatibility with design environments.The Web-based interface allows the user to remotely access and execute the simulator using his/her own Webbrowser (without the need of any software installation).

We present a new gate-level approach to current simulation. We use a symbolic model of current pulses that takes accurately into account the dependence on the switching conditions. We then construct current waveforms during event-driven logic simulation by means of pulse composition. We obtain satisfying accuracy on time-domain current waveforms and on peak current estimates, while maintaining performance comparable with traditional gate-level simulation.

This paper addresses the problem of the design of embedded two-rail checkers. In particular a simple additional circuit is proposed which can be used to make a two-rail checker receive all the codewords of the two-rail code, independently of which and how many codewords are produced by its driving functional block or checkers. The proposed circuit features a high online self-testing ability with respect to possible internal faults and a compact structure.

This paper presents new algorithms for evaluating the reliability of fault-tolerant combinational logic circuits. In order to model the effects of multiple faults on circuit functionality, we use fault indicators as control variables. We use BDD-based symbolic simulation to avoid the explicit enumeration of faults. We present experimental results on fault-tolerant implementations of several mcnc benchmark circuits. They show that undetectable multiple faults have a large impact on the reliability of fault-tolerant circuits.

This paper presents a study of the dynamic behavior of CMOS and BiCMOS digital circuits induced by bridging faults, whose resistance value is shown to have a strong impact on the dynamic behavior of faulty gates and of their fan-out gates. The problem of fault detection is addressed considering delay fault testing and results are compared with those achieved by means of functional testing. Electrical simulation has been used to investigate the main differences between BiCMOS and CMOS circuits. It is shown that, because of the large driving capability of BJTs, the detection as delay faults of bridging faults in BiCMOS circuits is more difficult than in the CMOS case.>

A numerical method for the determination of isotropic band models has been developed and applied to silicon. The resulting model accurately approximates both density of states and group velocity of the corresponding anisotropic band structure, thus providing an excellent agreement with both the collision and nonhomogeneous terms of the Boltzmann transport equation. The model, represented by a simple set of energy-wave vector tables, has been implemented in a Monte Carlo device simulator, but can also be extended to alternative methods for solving the Boltzmann equation. Simulation of homogeneous silicon shows a very good agreement with available experimental data. Comparison with results obtained using the complete anisotropic band structure, both in homogeneous and nonhomogeneous silicon devices, confirms the validity of the model.>

The authors point out that the simulation of resistive bridging faults inside complex CMOS macrogates requires proper evaluation of resistances, in order to correctly determine realistic fault coverages. Here, an approach applicable to a large category of faults (bridgings, transistor stuck-ons, and node stuck-ats) that give rise to resistive paths between power supply and ground, and hence are all covered by the general term 'bridging faults,' is presented. This method, which avoids the single-fault-injection procedure, fault analysis is performed inside the macrogates aimed to determine the threshold resistance, thus discriminating whether or not a given fault is detectable as a logic error. This analysis is performed inside CMOS macro-gates whose output is observable. To fully characterize the quality of a test sequence with regard to resistive bridging faults, a new definition of fault coverage is presented, because the common concept of fault detection is not applicable to parametric faults.>

This paper presents a study of the effects on the electrical behavior of BiCMOS digital circuits induced by bridging faults, whose resistance value is shown to have a strong impact on the static and dynamic behavior of faulty gates and of their fan-out gates. The problem of fault detection is addressed considering different testing techniques (current monitoring, functional, and delay testing). Electrical simulation has been used to investigate the main differences between BiCMOS and CMOS circuits. It is shown that, because of the large driving capability of BJTs, the detection of bridging faults in BiCMOS circuits is more difficult than in the CMOS case when functional or delay testing is used whereas it becomes more effective when adopting current monitoring.>

This paper presents a new approach to the fault simulation of parametric bridgings in CMOS ICs synthesized by means of libraries of macro-gates. The method is based on a fast but accurate preliminary characterization of any macro-gate for each input set. Such a characterization provides all information to determine, during the actual fault simulation, the maximum value of resistance for any considered bridging that makes the fault observable at a circuit primary output. This library characterization is very general, and can be used with any fa.ult simulation technique. Results on several benchmarks show that this approach allows the fault simulation of internal parametric bridging faults in a time comparable to that of the classical line stuck-ats.

This paper analyzes the effects induced on the electrical behavior of BiCMOS digital circuits by bridging faults, whose instrinsic resistance value is shown to have a strong impact on the static behavior of faulty gates and of their fan-out gates. The problem of fault detection is then addressed considering two different testing techniques (current monitoring and functional testing). Simulations of the electrical behavior of faulty BiCMOS circuits have enlightened the main differences with respect to the CMOS technology: the larger driving capability of BJTs with respect to MOSFETs makes the detection of bridging faults much more difficult in BiCMOS circuits when functional testing is considered, but more effective when current monitoring is used.

The authors present two methods for computing the fault detection probabilities in combinational networks. The methods provide a deeper insight into the effects of signal correlations caused by multiple fan-out reconvergencies and can be used in testability analysis to predict the fault coverage of pseudorandom patterns. The performances of these algorithms have been tested on significant benchmarks and compare favorably with those of previous procedures.>

A probabilistic approach to the detection of analog faults (i.e. transistors stuck-on and bridgings) in CMOS circuits that depends on the conductances of faulty and fault-free networks is presented. It is shown that unrealistic fault coverages can be obtained by simply assigning constant values to the conductances of transistors and bridgings and by comparing the resultant conductances of faulty and fault-free conflicting networks. To solve this problem, all conductances are considered as random variables with normal distribution. Conductance distributions of complex conflicting networks can be easily evaluated, and the detection probability of each fault is determined. The expected coverage of analog faults is known at the end of a fault simulation. This result is shown to be more realistic than those obtained in a deterministic way. Fault coverages of analog faults obtained by means of a gate-level fault simulator are discussed for a complex FCMOS benchmark.>

The authors present a theoretical investigation of the aliasing error probability (AEP) in signature analysis testing by means of linear finite state machines (LFSMs). The equations of the resulting Markov chain model of the LFSM are solved to determine an exact expression of the AEP as a function of the main LFSM features and of the relevant parameters of the testing environment. This expression is used to prove criteria for the synthesis of LFSMs with minimum asymptotic and transient AEP. A fundamental lower bound on the AEP is presented, which represents the performance limit of any LFSM with respect to aliasing minimization. It is shown that the AEP in machines realizing counters mod 2/sup k/-1 is the closest to such a bound, in particular periodically reaching it.>

The authors present a novel technique to study the detection of non-stuck-at faults in CMOS circuits. Gate-level models of CMOS faults not yet adequately covered in the literature are developed. Suitable models for transistor stuck-open and stuck-on, gate-drain shorts, and bridgings are implemented in a fault simulator. Results obtained with typical circuits are presented and discussed to analyze the influence of circuit architecture and type of test vector (deterministic or pseudorandom) on the coverage of non-stuck-at faults. The following general conclusions are drawn from these results: (1) shorts between transistor gate and drain are adequately detected by stuck-at oriented test patterns, and, hence, they do not represent a significant problem in IC testing: (2) the coverage of transistors stuck-open is significantly dependent on the test pattern generation method used; (3) the detectability of bridgings depends strongly on the circuit topology; and (4) the indirect coverage of transistors stuck-on is inadequate, essentially because a large number of them are undetectable.>

A novel fault grading heuristic is presented, based on the critical path tracing technique that tackles the problems associated with fan-out reconverging nodes (FORNs) without using forward propagation of the fault effects. To determine the criticality status of a fan-out reconverging node, which can differ from that of its fan-out branches (FOBs), the concepts of evidencing and masking paths are used. Using the statistics from exact fault simulations, heuristic rules are derived for the generation of masking and evidencing paths. The results obtained on benchmark circuits show good accuracy for fault coverage estimates and a computation time linear in the number of gates and comparable to that of the fault-free simulation.>

Monte Carlo simulations of high-energy electrons and holes in Si n-MOSFETs are presented. Key features of this work include the use of a suitable silicon model for carrier transport at high electric fields, an original impact ionization model, and sophisticated numerical techniques to speed up the calculation. The case of submicrometer Si n-MOSFETs is considered as a relevant application.>

An improved, more complete strategy for latch-up testing of CMOS ICs is proposed in order to take into account important effects that have been neglected by standard procedures, but which are shown to reduce considerably the circuit resistance to latch-up. These phenomena include interactions among carriers injected by different p-n-p-n structures, voltage drops on power supply and ground lines caused by output pin load currents, and effects of power supply voltage and chip heating. All experiments with regard to this work have been performed by means of automatic test equipment, which provides the possibility of completely controlling the circuit state and operating conditions during testing.>

An investigation of the properties of multiple input shift registers for signature analysis is presented. The assumption of independent errors at the register inputs has been used to model the register behavior as a Markov process whose equations have been solved to obtain the exact dependence of aliasing probabilities as a function of test length, input error probabilities, and feedback structure. Some unique featured of maximum-length registers are proven. Accurate simplified expressions of aliasing probability are derived for use as tools in the evaluation of the coverage.>

Two methods for the calculation of fault detection probabilities in combinational networks are presented. These methods provide a better accuracy than existing algorithms and a deeper insight into the effects of first order correlations to multiple fan-out reconvergencies. These techniques have been applied to standard benchmarks as well as to a few commercial circuits and have shown to provide a significant improvement compared with existing methods with minimal drawbacks in terms of required computing resources.>

Novel design-for-testability schemes are suggested to improve the detectability of transistor stuck-on faults, bridgings, and gate oxide shorts in CMOS digital circuits, with limited extra hardware and minimum degradation of circuit performance. One of the techniques makes analog faults detectable by observing the circuit outputs just as for stuck-ats. Also described is a technique in which the gates are modified with the insertion of n-channel FETs whose drains are the input of a ratioed NOR testing logic realized with n-channel drivers and a single resistive p-channel pull-up device.>

The authors present a testing method for monitoring E/sup 2/PROM (electrically erasable programmable ROM) cell aging. The technique is not based on any particular assumption about cell technology: hence it can be used to characterize wearout dynamics in all cases in which charge trapped in tunnel oxide is the main failure mechanism. The method is validated by means of a wide set of measurements performed with automatic test equipment. The characterization can be directed to single cells, thus making it possible to study the main layout dependences of aging phenomena. Possible criticalities of the virgin devices (with respect to supply voltage temperature, etc.) can be determined. A procedure has been developed to extrapolate data obtained with a few programming cycles in order to obtain first-order estimates of the actual device endurance.>

Exact expressions for the aliasing error probability in multiple-input shift register for signature analysis testing are derived and used to obtain criteria for the optimal synthesis of signature registers. The register behavior is modeled under the assumption of statistical independence of error vectors from the circuit under test (CUT). A general solution to the resulting Markov chain is presented on the basis of an original coding theory technique that clarifies the effect of the major register features, as well as of the correlations among the CUT output bits. It is then possible to analyze in detail the most important design issues, such as the choice of the feedback polynomial and of the register optimal structure.>

The Markov chain model of linear feedback shift-registers (LFSRs) for signature analysis testing is analytically solved to obtain the exact expression of the aliasing error probability as a function of test length, error probability, and the structure of the feedback network. The dependence on feedback configuration is explored in depth, and it is proven that maximum-length LFSRs have the best performances with respect to aliasing, regardless of the particular structure of their feedback network. Simplified expressions of aliasing probability are also derived for use as practical tools to design LFSRs for IC signature analysis testing, and a heuristic criterion is given for the identification of peaks in aliasing probability.>

An efficient self-consistent device simulator coupling Poisson equation and Monte Carlo transport suitable for general silicon devices, including those with regions of high doping/carrier densities, is discussed. Key features include an original iteration scheme and an almost complete vectorization of the program. The simulator has been used to characterize nonequilibrium effects in deep submicron nMOSFETs. Substantial overshoot effects are noticeable at gate lengths of 0.25 mu m at room temperatures.>

The authors present an accurate model of aliasing probability in signature analysis testing, based on the assumption of independent error bits, that makes it possible to treat the statistical behavior of the register as a Markov process. A proof is given that minimum-hardware registers realizing maximal counting sequences represent optimal choices for aliasing minimization. Exact as well as simplified expressions of aliasing probability have been derived, and a criterion for the identification of maximal aliasing conditions is presented to be used as a tool for the choice of optimal test length.>

An efficient Monte Carlo device simulator has been developed as a postprocessor of a two-dimensional numerical analyzer based on the drift-diffusion model. The Monte Carlo package analyzes real VLSI MOSFETs in a minicomputer environment, overcoming some existing theoretical and practical problems. In particular, the particle free-flight time distribution is obtained by a new algorithm, leading to a CPU time saving of at least one order of magnitude compared with the traditional approach. To describe rare electron configurations, such as the high-energy tails of the distributions and the particle dynamics in the presence of large retarding fields, a multiple repetition scheme was implemented. Selected applications are presented to illustrate the simulator's capabilities.>