This work presents the hardware design of a dynamically reconfigurable function unit (RFU) to accelerate computation-intensive tasks in Medium Access Control (MAC) layers of WLANs. The function unit is integrated in a pipelined 32 bit RISC processor and provides full hardware support for the Advanced Encryption Standard (AES) as specified in upcoming WLAN standards such as IEEE 802.11i. Dynamic reconfiguration allows the processor to use arithmetic components and memory elements of the RFU not only for AES, but also for additional tasks common in the MAC-layer. With our approach it is possible to accelerate Reed-Solomon-Code generation, Cyclic Redundancy Checks as well as other encryption standards like SQUARE, Magenta and Twofish by supporting Galois Field multiplication and table look-ups. The integration of the reconfigurable unit in the processor core results in an architecture that can simultaneously support control-flow and data-flow oriented tasks. This architecture was prototyped onto a Virtex2 FPGA.

This paper focuses on the reconfiguration requirements of hardware platforms for high speed wireless communication systems. Due to the underlying trade-off between flexibility and efficiency, many reconfigurable hardware solutions and FPGA implementations are prone to significant energy and performance penalties in comparison to application specific hardware designs. These penalties can only be alleviated by designing reconfigurable architectures for selected applications fields, since each application field has only a limited set of flexibility requirements. In this paper the analysis is conducted for emerging wireless communication standards based on the OFDM (Orthogonal Frequency Division Multiplexing) or CDMA (Code Division Multiple Access) transmission technique. The requirements for the physical and the medium access layers are analyzed separately. Focus is also set on different market segments.

Because of the increasing importance of cross coupled capacitances in deep submicron technologies, it is of great interest to extend the existing high-level power estimation techniques by considering the spatial correlation between adjacent lines. This work addresses the modeling and estimation of power dissipation in on-chip buses based on the statistical properties of data sequences. Using the derived models, a power estimation technique is proposed and evaluated for various coding schemes. For different DSP applications, our results depict less than 5% discrepancy with precise bit level estimations.

Because of the increasing demand of portable digital systems, it is of great interest to extend the existing high-level power estimation techniques to handle architectures with non linear components, as they appear in relevant practical applications. In this paper we focus on the estimation of the transition activity in MAC structures implementing FIR filters. Based on a divide and conquer approach, an accurate yet efficient estimation procedure is developed. The technique has been evaluated for different synthetic and real data sets. In all cases, our results depict only very slight discrepancies with respect to precise bit level simulations.

The performance of a packet-oriented OFDM system relies strongly on the goodness of the synchronization scheme. In practice, the theoretical accuracy of a synchronization technique can be worsened by the finite-precision effects introduced the digitization of signals. This work evaluates the impact of the quantization errors on the performance of the coarse timing synchronization and CORDIC (COordinate Rotation DIgital Computer)-based frequency compensation for OFDM burst-mode applications. Furthermore, an analytical approach allowing one to predict the wordlength according the required accuracy degree is proposed. Simulation results related to the application of this evaluation scheme to the HiperLAN/2 environment are presented.

A tight lower bound on the accuracy of CORDIC (coordinate rotation digital computer) based frequency offset estimation and correction schemes is derived. The evaluation scheme relies on the Cramer-Rao lower bound (CRLB) and the upper bound of the error introduced by the CORDIC algorithm. Simulation results related to the application of the bound to a HIPERLAN/2 simulation model are presented.