An integrated BCD gate driver employing adaptive dead-time control (ADTC) and a compact gate-boost (GB) circuit is presented. The ADTC reduces both dead-time intervals from conventional$\sim 10 ~\text{ns}$to a nearly load-independent high-to-low dead time$\left(D T_{F}\right)$of$0.7-1.2 ~\text{ns}$over$1-6 ~\mathrm{A}$, and digitally minimizes low-to-high dead time ($D T_{R}$) to$\sim 1 ~\text{ns}$, lowering bodydiode conduction and reverse-recovery losses. At$38 ~\mathrm{V}, 6 ~\mathrm{A}$, and 2.2 MHz, this recovers a combined dead-time loss of up to 1.47 W, yielding an efficiency gain of 1.81 %. In addition, the open-loop GB circuit accelerates the later stage of the high-side transition, halving the$L X$rise time (28.4 ns to 14.5 ns) and yielding an additional 1.09 W loss reduction and 1.33 % efficiency gain. Overall, the proposed solution achieves a total loss reduction of 2.56 W and a 3.14 % absolute efficiency improvement.

This paper proposes the first simultaneous wireless power and data transfer (SWPDT) integrated circuit (IC) which exploits a Capacitive-Inductive Channel (CI-Channel), enabling concurrent power and data transmission. The communication across the CI-Channel can support data-only transmission or can be incorporated into the system control loop, allowing output voltage regulation through phase-shift control applied at the primary side. The proposed IC can be configured as primary side (power transmitter, P-TX, and data receiver, RX) or secondary side (power receiver, P-RX, and data transmitter, TX). In order to ensure communication robustness, unwanted disturbances are removed through specifically designed Power Blanking and Ringing Blanking circuits. The proposed SWPDT IC test-chip prototype was fabricated using a 130-nm BCD process and experimentally verified considering the complete wireless power transfer (WPT) system, including primary side, CI-Channel and secondary side. The overall system, targeting medium-power industrial applications, achieves a maximum 5.3-W output power, a peak efficiency of 83.7% and a load regulation of 0.09 mV/mA. Moreover, a 540 kb/s data rate with no transmission errors across$10^{9}$bit acquisitions, corresponding to a bit-error-rate (BER)$\lt 10^{-9}$, was achieved.

A high-speed, low-figure-of-merit capacitive floating level shifter (CF-LS) for high-side bootstrapped gate drivers is presented. The design integrates a feedback discharge control (FBDC) for enhanced$V {_{\text {SW}}}$dV/dt (SRSW) immunity and combines a mismatch reduction circuit (MMRC) with a common-mode blanking pulse (CMBP) to block common-mode (CM) signals with mismatch. Fabricated in a 0.75-$\mu $m STMicroelectronics bipolar-CMOS-DMOS (BCD) process, the proposed CF-LS occupies 0.048 mm2with the core area being 0.026 mm2, making it highly compact and integration-friendly. It achieves a propagation delay ($T {_{\text {P}}}$) of 1.525 ns and transition energy ($E_{T}$) of 29.77 pJ at 40 V, both of which remain approximately constant across the$V {_{\text {SW}}}$sweep from 0 to 40 V, while maintaining measured SRSWimmunity of up to 20 V/ns and mismatch tolerance up to 30%. Compared to recent works, the design offers a$2\times $improvement in figure-of-merit2 (FoM2), achieving 2.68 ns$\cdot $pJ/$\mu $m${^{{3}}} \cdot $V at bootstrap supply ($V {_{\text {BS}}}$) of 5 V, and$3\times $improvement when supplied at 3.3 V. The CF-LS has been comprehensively validated both as a standalone circuit and when integrated within a dc–dc buck converter, making it a highly robust, efficient, and versatile solution for high-frequency power management systems operating up to 55 MHz.

This paper tackles the issue of control loops in high-frequency switching-mode DC-DC buck converters for post-regulation in automotive applications. Two different control loop implementations, designed in a 120-nm BCD process, are proposed and verified through simulations. Both solutions exploit the advantages of standard voltage mode control (VMC), while improving the transient response by including a one cycle (OC) and a feed forward (FF) loop, respectively. The OC VMC loop achieves 0.92 mV/V line regulation and 0.6 mV/A load regulation, whereas the FF VMC attains 0.17 mV/V line regulation and 4.8 mV/A load regulation, thus both outperforming the state-of-the-art of high-frequency switching-mode buck converters.

This paper introduces a dynamic current comparator employing a parasitic charge recycling technique to achieve an ultra-low energy per comparison of 175 fJ. Furthermore, incorporating a switched capacitor supply in the static portion of the circuit, the comparison energy is further reduced to 55 fJ, more than three times lower. The proposed circuit, designed and extensively simulated in a 130-nm CMOS process with thick gate MOS transistors, demonstrates a comparison time of 3.8 ns, with a 100-nA input difference and a 32-MHz clock, while offering an input-referred noise of 2.9 nArms. These features make the proposed comparator highly suitable for medium-to high-resolution data conversion systems, particularly in biomedical and sensor-readout applications. Additionally, it is well-suited for high-speed and cryogenic CMOS systems, where current-mode architectures are becoming increasingly relevant.

A 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) in 180-nm CMOS is presented. Designed for the readout of inertial sensors in micro-electromechanical systems (MEMS) technology, it combines an asynchronous control scheme with a 2-bit per cycle architecture achieving enhanced energy efficiency. Operating at a 1-MS/s sampling rate, the proposed ADC draws 8.9-µA of total current from a 1.8-V supply. Additionally, it demonstrates an SNDR of 63.2 dB across the entire Nyquist bandwidth, resulting in a Walden figure-of-merit (FoM) of 13.6 fJ/conv-step. The achieved energy efficiency makes the proposed ADC suitable for battery-powered applications requiring medium resolution and data rate.

High-performance linear LED drivers for RGB applications rely on an accurate current generation to achieve the desired luminous intensity or color accuracy. Random hardware faults are a class of malfunctions that can occur during the lifetime of a device, like for example: a bonding failure, an excessive device aging leading to large MOS threshold drift, gate-oxide shorts, etc. For LED drivers, random faults are detected by monitoring the output current. The random fault coverage (RFC), i. e. the percentage of random faults that can be detected by the hardware dedicated to the monitoring function, can be surprisingly low if the current monitor is not specifically designed for this goal. This paper presents a novel current monitor, based on a cascode structure as a sensing element and fabricated in a conventional 180-nm CMOS process, capable of achieving an RFC of 90%. This remarkable result is obtained with an area overhead of only 8.5% with respect to a conventional approach.

This paper presents a Current-to-Digital Converter (CDC) designed for Computed Tomography (CT). The circuit, featuring a fully differential architecture, has been fabricated in a 0.35-µm-CMOS technology with a silicon area of 0.65 mm2and consumes 300 nJ per conversion from a nominal supply voltage of 3.3 V, with a conversion period of 200 µs. The average power consumption is reduced by 22% by applying a dynamic power consumption scaling technique based on operational amplifier slicing. The proposed CDC achieves a dynamic range of 89 dB (12.75 ENOB) over a 2.5 kHz bandwidth, leading to a Schreier figure-of-merit of 151.2 dB.

This paper proposes a three-stage operational transconductance amplifier (OTA) with slew-rate enhancing, especially designed for interfacing triboelectric nanogenerator sensors in smart textile applications. The proposed OTA, designed in a 130-nm BCD process, features 0.015-mm2area and 2.7-µW power consumption with 1.3-V supply voltage, while meeting the specifications of the targeted application, thus constituting a very compact low-power low-voltage solution. The proposed OTA was extensively simulated with Cadence Virtuoso, verifying its post-layout performance and robustness against process, voltage and temperature (PVT) variations.

A high-speed low-figure-of-merit capacitive-coupled level shifter tailored for high-side bootstrapped gate drivers is presented. Key techniques include a Feedback Discharge Control (FBDC) for improved dV/dt Immunity, a MisMatch Reduction Circuit (MMRC) in combination with Common-Mode Blanking Pulse (CMBP) to block common-mode signals with improved mismatch tolerance. The level shifter is fabricated in a 0.75µm STMicroelectronics BCD process and covers a chip area of 0.048mm2. Experimental results demonstrate a Propagation delay (TP) of 1.525ns and Transition Energy (ET) of 29.77pJ at 40V, with a dV/dt immunity of up to 20V/ns. The level shifter achieves a figure-of-merit 2 (FoM2) of 2.68ns.pJ/um3.V, an improvement of 2x from the recent literature, and exhibits a mismatch tolerance of 20%. The design has been tested at a switching frequency (FSW) of up to 55MHz. The design is validated through standalone and integrated testing in a DC-DC buck converter.

High-speed dynamic latch comparators are integral part of the state-of-the-art ADCs. This work presents a configurable dual-mode voltage comparator using a supply boosting technique. The power dissipation of the comparator is proportional to the square of the supply voltage. Hence, the comparator is configured to operate at a supply voltage of 0.9 V under normal operating conditions. During high-performance mode, when the input differential voltage is small, the supply voltage is boosted to 1.5 V, satisfying the power-delay trade-off. The architecture is designed and simulated in a 180-nm CMOS technology with a supply voltage of 0.9 V. The increased supply voltage of 1.5 V is generated internally using a switched capacitor technique. The power consumed at 0.9 V and 1.5 V is 0.4 mW and 1.29 mW, respectively. The simulated offset at ΔVIN= 1 mV in Mode = 0 and Mode = 1 turns out to be 4.05 mV and 3.14 mV respectively.

This paper focuses on control techniques for an integrated Dual Active Bridge (DAB) converter designed for low-voltage (5V) and low-power (2W) applications. The analysis concentrates on the single-phase-shift (SPS) modulation, as it offers the best balance between implementation simplicity and power efficiency for a control loop circuit that must be embedded within the system. Moreover, an innovative modulation technique called controlled single-phase-shift (CSPS) is introduced, which dynamically adjusts the phase-shift to maximize current flow through the load. This approach enhances the output power range by 33%, achieving an increase in the average efficiency throughout the phase-shift interval up to 4% when compared to the conventional SPS modulation. Circuit-level simulations have been conducted in Cadence Virtuoso environment to verify the effectiveness of the proposed approach.

This paper introduces a quasi-passive Noise-Shaping Successive Approximation Register Analog-to-Digital converter (NS-SAR ADC) suited for low power Audio Activity Detection (AAD). Exploiting a 2ndorder Error-Feedback (EF) loop filter implemented through a low power open loop amplifier, insensitive to Process-Voltage-Temperature (PVT) variations, and a fully passive Charge-Sharing (CS) summing node, this converter reaches 78 dB of Dynamic Range (DR), achieving a Schreier Figure-of-Merit (FoMs) of 165.3 dB. Fabricated in a 65-nm BCD process, the proposed ADC core occupies 0.129 µm2consuming 14.9 µW from a 1.2-V supply.

This paper presents a monolithic GaN current sense circuit designed for the high-side of a 100-V half-bridge. The circuit is engineered to minimize current offsets and response times across a wide range of input voltages (10 V to 100 V), as well as varying temperatures and current loads. It is capable of tracking inductor current ripples and detecting the zero-current condition of the half-bridge high-side power transistor. The proposed solution demonstrates a simulated loop gain exceeding 100 dB and a bandwidth of 43.9 MHz, which achieves an accuracy of 99.4% and a response time of 145 ns under operating conditions of 50-V input voltage, 10-A current load, and 27°C.

This work presents the design of a bipolar junction transistor (BJT)-based temperature sensor with a sigma-delta analog-to-digital converter ($\Sigma \Delta $ADC) fabricated in a 0.6$\mu $m BiCMOS process. The sensor utilizes a proportional to absolute temperature (PTAT) current source embedding an auto-zeroing amplifier to bias the BJT core while effectively reducing offset errors. Additionally, this work achieves the combination of the temperature-sensing BJT core and the$\Sigma \Delta $modulator, utilizing dynamic element matching (DEM) technique to accurately generate three different ratios (1:9, 9:1, 5:5) of BJT bias currents to cooperate with the modulator for modulation. The innovative modulation method in this work can reduce the errors caused by the operational amplifier offset voltage and BJT mismatch, completing the digitization of temperature without the need for a reference voltage source. Moreover, the sensor integrates a complete digital signal processor (DSP), allowing on-chip calibration by adjusting the operating cycle of the modulator and the initial value of the counter to obtain accurate and directly readable temperature data. It operates under a 3.3 V supply within a temperature range from −50 °C to 125 °C. Lastly, it achieves a 17 mK resolution and an inaccuracy of ±1.5 °C (3$\sigma $) after an on-chip single-point calibration.

This paper focuses on the impact of segmentation on the linearity performance of gigasample rate current-steering digital-to-analog converters (DACs). The effect of their output impedance drop and code-dependency occurring at increasingly higher data rates is studied with the purpose of deriving relevant design constraints about the segmentation scheme choice. This analysis is supported by extensive simulation results carried out with special attention to the spurious-free-dynamic-range (SFDR) and third-order-intermodulation-distortion (IM3) metrics. Lastly, a 10-bit 6.4 GS/s DAC designed in a 55-nm BiCMOS technology is presented and discussed in relation to the previously determined scenarios. Besides featuring a 65.9-dBc SFDR at 1 GHz and an IM32.

This paper presents the system-level discussion, simulation design, and fabrication results of a novel analog ASIC - fabricated in 130nm BiCMOS technology - for interfacing resistive thermal sensors known as Fly Height Sensors (FHSs). FHSs are attached to the magnetic recording heads in modern hard disk drives (HDDs) to monitor the head-disk distance known as “fly height” by measuring the FHS resistance variation. The magnitude of the sensor signal serves as a measure of the proximity between the head and the disk surface which must accurately be controlled to minimize the fly height, thereby increasing the storage capacity of HDDs. The proposed interface includes two parts: 1) a dual-mode precise bias circuit that accurately provides a differential bias with a programmable common-mode voltage to the FHS in both voltage (V) and current (I) modes without requiring any calibrations, as well as featuring fast and smooth transient response, 2) front-end gain stages that create two separate signal paths with low- and high-frequency responses, called LF and HF blocks, utilized for controlling the fly height and mapping the roughness of the disk surface, respectively. The proposed bias circuit demonstrates high-impedance loading behavior on the sensor terminals in both V- and I- modes to have a unity signal gain at the sensor port and deliver it to the front-end amplifiers, resulting in an improvement of the overall noise performance of the interface. In addition, the bias noise power at the output of the LF block is suppressed to the extent of one order of magnitude thanks to deploying a noise cancellation technique. A low-noise and wide-bandwidth front-end is implemented for the HF block that eliminates the need for configuring the bias loop for having a low cutoff frequency, resulting in a reliable design with reduced complexity. Additionally, degenerated differential pairs with resistive loads, split tail currents, and Caprio’s quad offering low gain variation over the temperature and process are implemented as the front-end gain stages. The fabricated chip features an active area of 1.28 mm2with power consumption in the range of 110 to$172~mW$for the V-mode and 78 to$107~mW$for the I-mode, considering typical supply voltages of$+3.3\; V$and$-2.6 \;V$, and the sensor resistance ($R_{SNS} = 75\; \Omega $) and the sensor current ($I_{SNS}$) from 0.5 to$6\;mA$.

This paper presents an energy-efficient level shifter, which up-convert to 1.2 V from 0.3 V. The proposed architecture is based on single-stage differential cascode voltage switch logic (DCVSL) with multi-threshold transistors. A self-adapting pull-up (PU) network is used, which increases the switching speed and reduces energy consumption. To further improve the energy efficiency, a split-input inverting buffer with a higher threshold voltage is used in the output stage. The proposed design is implemented in 65 nm CMOS technology for$V_{DDL}=300\text{mV}$and$V_{DDH}=1.2$V. To up-convert from 0.3 V to 1.2 V, the proposed architecture has an average propagation delay of 11 ns and achieves 3.85 fJ of energy per transition at 1 MHz operating frequency.

This paper presents a Class-D audio amplifier, fully compatible with standard BCD technologies, that features in the direct signal path an ADC ($\Sigma\Delta$modulator), a digital third-order loop-filter and digital PWM. The overall closed-loop mixed-signal architecture pushes most of the signal processing towards the digital domain, thus allowing the use of scaled technologies to reduce cost and size. Moreover, the high gain developed by the digital filter and by the integrator inside the$\Sigma\Delta$modulator, attenuates the residual high frequency ripple around the loop and concurrently improves the THD+N in the audio band. In this paper the feedback is closed after the output LC filter, thus mitigating the influence of its components on the amplifier transfer function and on the linearity. The proposed architecture achieves in simulation 120 dB of SNR and a THD of 0.01%-0.001 %, even in wide input signal conditions.

This paper presents a novel capacitive-inductive structure implementing the channel for power and data transmission in a wireless power transfer system. The structure consists of two$24-\mu\mathrm{H}$coil inductors, each surrounded with an open ring copper layer realized on a printed circuit board (PCB). The proposed channel structure allows simultaneous transmission of power and data: indeed power is transferred through the magnetic field generated by the coils, while data are modulated and transferred through the electric field produced by the capacitance determined by the copper rings and the parasitic capacitance of the two coils. The proposed structure was extensively studied and characterized both through simulations and measurements: compared to the state-of-the-art, in which metal plates placed below the coils are employed for implementing the capacitance used for data transmission, it shows a significant decrease in parasitic capacitance between the copper ring and the coil, thus reducing power disturbances on the data transmission.

This paper proposes a time-domain-based architecture for implementing a bandgap reference: indeed, the proportional-to-absolute-temperature (PTAT) voltage is provided by subtracting the gate-to-source voltages ($V_{GS}$) generated in two subsequent phases by the same diode-connected NMOS device, operating in subthreshold region and biased at different currents. As the same transistor is employed in both phases for the PTAT voltage generation, mismatch effects are inherently reduced. The proposed bandgap reference combines the PTAT and the complementary-to-absolute-temperature (CTAT) voltages by means of a switched capacitor difference amplifier and, if required, includes a dedicated sampling and filtering circuit. It features 5-bits trimming and implements curvature compensation through the addition of an integrated resistor with appropriate temperature dependence to the CTAT branch. The proposed bandgap reference circuit was designed in a standard 130-nm CMOS process and was extensively simulated in Cadence Virtuoso, achieving a worst-case 0.756-ppm/°C temperature coefficient.

This paper presents a SAR-assisted first order incremental$\Sigma\Delta$analog-to-digital converter (ADC) equipped with an accumulation based sample and hold (S/H) circuit to effectively limit its kT/C noise contribution, potential bottleneck for the resolution performance of the converter. This system has been designed for shunt current measurements in the electrical drives battery management framework; the sensed and digitized current information is needed for a proper monitoring and regulation of the behaviour of these essential devices for automotive applications. The converter has been developed at the behavioural level in the MATLAB Simulink environment with special attention to the S/H circuit which has been analyzed in Cadence Virtuoso; the complete system features a high common mode voltage (HCMV) in the order of tens of Volts, a peak-to-peak 50 mV differential input range and a target resolution of 12 bits.

This paper presents a trimming technique to suppress the thermal effects of process spread of BJT-based temperature processing circuits. The proposed calibration method has the advantage of requiring a reading at a single temperature while compensating for the spread of the thermal behaviour of the base-to-emitter voltage of bipolar transistors; in addition to this, the effectiveness of the proposed technique is improved by an exponential approach carried out on the design of the trimming structure. The strength of the presented technique is shown to be effective on a 6-bit trimming circuit designed and extensively simulated in a standard 180-nm CMOS process; this implementation provides a reduction of the considered spread of about 90% making it suitable for a number of applications in which process variations limit the accuracy of the circuit.

This paper presents a novel micromachined high-responsivity thermopile sensor, fully compatible with standard CMOS-SOI (Silicon-On-Insulator) processes. The proposed thermopile features a versatile mosaic structure, based on 128 60 μ m × 60 μ m pixels connected in series and/or in parallel. Two versions of the proposed thermopile sensor, featuring a different number of equivalent pixels, are presented and fully characterized. The most performing of the two features $2.9\cdot 10^{4}\frac{V}{W}$-responsivity, outperforming other state-of-the-art thermopile sensors. The application of the most performing thermopile as proximity and motion detector was also verified through measurements.

This paper presents a microsystem suitable for contact-less human body temperature measurements, as well as for presence, motion and proximity detection. It consists of a 130-nm CMOS-SOI MEMS (Micro-Electro Mechanical System) thermal sensor, referred to as “TMOS”, and its 130-nm CMOS interface circuit. The TMOS, based on a micromachined transistor, being an active device, features advantages in terms of internal gain: with optimal biasing, indeed, the TMOS achieves 274-$\mu \text{V}/^\circ \text{C}$input-referred sensitivity at 3-cm distance and 50.33° field-of-view (FOV), outperforming thermopile detectors. The sensor and the interface circuit, featuring a chopper-stabilized-based analog readout with a 12-bit SAR ADC (Successive Approximation Register Analog-to-Digital Converter), were mounted in the same package and extensively measured: the microsystem achieves repeatability and ±0.17°C precision, thus satisfying the requirements for contact-less human body temperature measurements; furthermore, its performance as presence, motion and proximity detector was also verified.

This paper proposes a dual ramp, pulse position modulation analog-to-digital converter. A delay cell is proposed in this work, which converts the timing information into a thermometric code. The proposed architecture uses a dual ramp, which initiates the time to digital quantization from both Most Significant Bit (MSB) and Least Significant Bit (LSB) ends. It requires the use of two current sources at both the ends resulting in more symmetrical non-linearity behavior compared to single-ramp architecture, thus improving the INL of the ADC. This technique leads to an increase in the sampling frequency by a factor of 2. It is designed and implemented in a 65-nm CMOS technology with a supply voltage of 1-V. The proposed ADC achieves an effective number of bits of 4.49 bits at a sampling rate of 100 MHz.

This paper describes the design and the performance comparison of four different configurations of power stages of switching DC-DC buck converters with high switching frequency (f = 100 MHz), studied for automotive applications in the post-regulated domain. Different transistors are used for both power stage and pre-driver chain, and the solutions are compared in terms of efficiency and maximum input voltage. A rough estimation of the area consumption of each of the four configuration is also provided. The circuits have been optimized to have maximum efficiency with V in = 3.6 V, V out = 1.8 V and I load = 1 A, which are typical values in automotive post-regulated applications.

Nowadays, the field of microelectronics has become the drive for the advancement of the times, which promotes new demands on the cultivation of the students in colleges and universities. In order to keep up with the trend of the global engineering educational reform, three important reforms in education have been in progress step by step, including classroom teaching, innovative training and virtual laboratories. At first, for enhancing and integrating the existing courses related to the circuit, so that the students can comprehend the existing knowledge much more effectively, an important and effective curriculum reform has been performed by combining “Circuit Analysis” and “Analog Circuit Foundation” into one course; Then, innovative training has been carried out to cultivate the team skills among the students; Finally, in consideration of the rapid development of the electrical and electronic experiment, the conventional laboratory equipment may not satisfy the demand of every student due to financial constraints, therefore, the construction of virtual simulation experiment center is an efficient way to break this bottleneck. As a result, the atmosphere of academic innovation of the pursuit of truth, advocacy of science, brave exploration, dare to practice have been formed in colleges and universities through the above innovative engineering education reform.

Evolution in consumer electronics has brought the need for high-current laser diode drivers (LDDs) compatible with integrated systems on chip (SOCs). Traditional solutions device-based are migrating to integrated architectures granting easy digital control, compliance to the voltage rails and fast switching times. The introduction of the digital control directly implies the need of digital-to-analog converter (DAC) structures for the modulation of the laser current and the chosen solution has to match the analog performances required for the particular application. This paper presents a current-mode DAC architecture for LDDs together with a 9-bit implementation which targets a rise time of 1.5 ns for a zero-to-full-current (51 mA) switching condition. A 0.105-mm2prototype has been manufactured in a 130-nm BiCMOS technology, and the experimental measurements are reported.

Multi-bit architectures of incremental converters are discussed. The use of a hybrid scheme and multi-rate operation reduces the consumed power. Methods for canceling or significantly reducing the error caused by the mismatch between unit capacitors are proposed. Behavioral simulation results prove the effectiveness of the solutions.

Advanced communication systems, smart and biomedical technologies have led to the need of complex laser systems. The traditional solutions, inherited by the traditional optical communication architectures, start to present limitations due to the high output compliance and high power consumption. Moreover, the common anode topologies present scarce adaptability to multi-purpose systems implemented in present systems on chip. This paper presents and discusses DAC architectures for a common cathode current driver suitable for laser system applications. The discussion is supported and complemented by results collected from simulations at the transistor level using a 0.13-μm BiCMOS technology.

This paper presents a readout circuit for thermopile-based thermal sensors, suitable for contactless temperature measurements. The circuit, designed and extensively simulated in a standard 130-nm CMOS process, employs chopper stabilization in order to minimize offset and noise contributions at low frequency, while providing proper amplification to the input signal, which behaves substantially as a DC. The circuit nominal supply voltage is 1.2 V and its power consumption is approximately 260 μW. The proposed single-ended architecture solves the drawbacks of the most straightforward fully differential approach, while achieving a simulated input-referred residual offset mean value equal to 84.4 nV, with 487 nV of standard deviation. An accuracy of ±0.3°C is provided at room temperature, making the circuit suitable for medical devices, such as contactless fever thermometers, and security systems, such as motion and human presence detection sensors.

This paper presents the design of an ultra high speed Flash ADC, designed in a 28-nm CMOS technology. The circuit exploits the metastability of the voltage comparators in order to enhance the converter resolution. The used technique allows achieving 5-bit of resolution with only 16 voltage comparators, reduces the input capacitance of the converter, lowers the power consumption and improves the area occupied. Clocked at 10 GHz, the obtained SNDR from post-layout simulations is 30.41 dB for an input signal of 900 mVpk-pkat 5 GHz. The simulated DNL and INL are within 0.3 LSB and 0.34 LSB, respectively. Consuming 55 mW, the achieved FoM is 0.21 pJ/conv-step.

This paper presents a lossy gyrator, which is used to implement a universal second order current mode filter. The proposed lossy gyrator uses conventional Second Generation Positive Current Conveyor (CCII+) as a basic building block, which has -3 dB bandwidth of 230 MHz and a total power consumption of 15.31 μW. A universal second order current mode filter is designed using proposed lossy gyrator, which achieves a high cutoff frequency of 18 Hz in low pass mode, a low cutoff frequency of 345 Hz for high pass, and a band pass response with resonating frequency at 90 Hz with a total power dissipation of 57 μW. Simulation is done using standard 180 nm CMOS technology at ±0.5 V supply voltage.

A method to calibrate the timing skew of flash-assisted time-interleaved analog-to-digital converters is proposed. The calibration is performed in two steps and is composed of a variance based and of an auto-correlation based timing-skew estimation. Both estimation phases are performed in the digital domain and require low hardware. In addition, channel randomization is facilitated with the use of the proposed method. Behavioral simulations have demonstrated that the method greatly improves the ADC performance and is effective up to the Nyquist frequency.

This study presents preliminary results of a broader research on Home Robot monitoring for elder people. The final goal of the project is the development of a robot that works in synergy with an automatic fall detection device, reaching the patient and checking his condition in case of triggered alarm. This paper covers the initial steps necessary for the design of the tracking network which provides the machine with the subject's position, in particular the single node performance. The network is based on Ultra-Wide Band (UWB) wireless transceivers that in this study are the Decawave EVB1000 evaluation boards. Two types of analysis have been performed on the anchor: a Line of Sight (LOS) baseline accuracy and interference robustness. The results demonstrate that, for LOS distance estimation, to achieve a margin of error below 15 cm, the node has to be closer than 12 m to the target. If we remove the line of sight condition, introducing a subject walking straight between the two anchors, the error is spread in the order of 10 cm from the original baseline for a 10 m nodes distance recording. If the path is obstructed instead by a subject walking perpendicularly to the nodes instead leads to a different types of perturbations, with an absolute error below 13 cm.

This paper presents an approximated linear model for memristive devices. Because of the abundance of technology solutions, the many models so far presented, more or less complicated, are generally technology-specific and this represents a problem for resistive memory designers who need to test the analog and digital periphery without affecting the computational costs. For this reason, an approximated model, formally derived from the traditional one, has been conceived and tested with a Verilog-A implementation. Based on the linear model, our approximation preserves a good fit with the experimental data, ensuring scalability and generality. Moreover, very important for memory applications, the computational costs and resources are considerably reduced. The model validity has been proven in some design cases, while model parameters have been extracted from measurements carried out on devices implemented in a 250-nm BiCMOS technology.

This paper presents two design considerations for integrated high-voltage DC-DC converters in automobile and industrial applications. The proposed solutions include (i) a quasi soft-start technique using over-current protection (OCP) circuits and limited duty cycle control and (ii) a technique to drive a floating load-side switch that suppresses the effect of bond-wire bouncing on its gate-source voltage. The first technique avoids the conventional, overhead start-up circuits and significantly reduces the converter startup time. The second technique gains importance primarily from device reliability viewpoint in high-voltage (HV) conditions. The effectiveness of the proposed techniques has been verified with simulations at the transistor level using a 110-nm BCD technology.

Battery operated IoT sensor based applications require low energy interfacing circuits. This paper proposes an auxiliary circuit, which works on the principle of level-crossing sampling, for such energy aware applications. This circuit generates a power enable clock for the ADC, one of the most power hungry blocks in IoT sensor interfaces. The auxiliary circuit is designed and simulated at the transistor level using a standard 180-nm CMOS technology. The effectiveness of the proposed scheme is demonstrated by using a 5-bit flash ADC as a study case. The proposed auxiliary circuit consumes only 3.52% of the total power budget including the test ADC.

This paper describes a novel sub-threshold voltage reference generator suitable for very low power and very low voltage wearable systems. Indeed, the circuit, designed and extensively simulated in a standard 0.18-μm CMOS technology, generates a 51.3-mV output voltage with a nominal supply voltage of 0.5 V and consumes as low as 185 nW. Design optimisation and a first order temperature compensation allow achieving a temperature coefficient of 25.4 ppm/ C in the temperature range from -40 to 125° C. The proposed architecture optimizes the output noise performance by minimizing the current mirrors flicker and thermal noise contributions which, in conventional schemes, severely affect the output node. In addition, the same circuital arrangement allows obtaining high power supply rejection (PSR). The simulated root mean square output noise is 1.6 μV in the frequency range from 0.1 Hz to 10 Hz, while the PSR is -76 dB at 100 Hz, a remarkable value.

This paper presents a level-shifting technique for high-voltage power converter applications. The proposed circuit effectively combines capacitive and active coupling of the input low (high) side signal to the output high (low) side to reduce the propagation delay of the level-shifting operation. By using the resulting circuit, (i) the high-side PMOS switch is driven at high speed and (ii) a quasi-zero voltage switching (ZVS) of the low side NMOS switch is achieved. The circuit has been designed and simulated at the transistor level using a 0.18-μm BCD process. At the high-side, remarkable simulated average level-shifter propagation delay and total driving delay have been achieved: 0.5 ns and 1.9 ns, respectively. The proposed level-shifter consumes 48.5 μA of average current.

This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is 1V and the simulated power consumption is 22.06 mW, which leads to a FoM of 32.4 fJ/conversion-step.

This paper presents the design of an hybrid course-fine time to digital converter for low power applications. The core of the circuit consists of two current-mode SAR analog to digital converters working in a time-interleaved fashion. The TDC has been fully simulated at the transistor level with a 0.13-μm CMOS technology. The paper discusses the design details and the digital calibration techniques required to achieve a single-shot resolution of about 27 ps while keeping the power consumption below 600 μW.

This paper describes a single op-amp 0+2 ΣΔ architecture and design considerations to achieve 12-b resolution on a 2-MHz bandwidth. The proposed topology combines op-amp reduction and MASH techniques. In particular, the second-order ΣΔ stage uses direct synthesis of the noise transfer function (NTF) and employs only one op-amp. The use of multi-bit quantization on both stages increases the resolution of the modulator and reduces the output swing of the op-amp. The mismatch of the multi-level DACs can be compensated for with DEM while the mismatch between the two stages can be canceled in the digital domain. Simulation results, carried out at the transistor level with a 0.18-μm CMOS technology, verify the effectiveness of the proposed architecture. The simulated FoM is 104 fJ/conv-step.

A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the input of the latch. The circuit has been implemented with a 28 nm FDSOI CMOS technology. Post layout simulation results show 8bit of resolution at 1.2 GS/s.

This paper proposes the use of sampled-data operation in op-amps. The technique favors very low supply voltage and micro-power. After discussing the method at a general level, a possible sampled-data scheme is analyzed. Simulations with a low threshold technology show that a 0.5-V supply is possible. A version of the circuit, which has been integrated by using a standard 0.18-μm CMOS technology (with high thresholds), is able to operate at 0.65-V supply voltage. Simulation results show 42.5 dB of DC gain and 2.5-kHz bandwidth with 0.5-pF load capacitor. The power consumption is 63 nW. A pseudo-differential scheme doubles the consumed power and increases the DC gain by 6 dB.

A magnetic Hall sensor working in the current-mode is presented. The proposed sensing device is composed by two Hall plates able to provide a differential current at the output nodes. The sensor, fabricated in a standard 0.18-μm CMOS technology, uses the spinning-current technique to compensate for the offset and obtains a sensitivity IHall/(B⊥Ibias) better than 0.02 T-1for magnetic fields ranging from 0 to 10 mT.

This paper describes a multi-bit third-order incremental analog-to-digital (ADC) architecture and design considerations to achieve 18-bit resolution. The architecture uses multi-bit quantization in order to increase resolution and reduce the output swing of op-amps. The non-linearity due to the mismatch of unity elements of multi-bit DAC is properly compensated for with Smart-DEM algorithm. This 2+1 incremental architecture achieves 18-bit resolution with a 3-bit quantizer. Simulation results verify the target resolution achieved with 61 clock periods despite a large unity element mismatch (3σ = 0.5%).

The Zigbee low-power communication standard has established itself as one of the most important wireless standards, enabling thousands of industrial and environmental monitoring applications. At the same time, Bluetooth and newly also Bluetooth Low Energy has captured the gadget and smartphone markets and currently enables various health and personal applications. The border between these two markets becomes thinner and applications would profit significantly from interconnecting these two standards and sharing the information obtained.

This paper presents the design of a third-order ΣΔ modulator targeted for WCDMA applications. The architecture uses two operational amplifiers and distributed fully digital feed-forward paths to minimize the output swing of op-amps. Simulation results show that first and second integrator output swings are reduced by 88% and 75%, respectively. Post-layout simulation results of the modulator, designed in 65-nm CMOS technology, give a SNDR of 83 dB over a signal bandwidth of 2.2 MHz. The power consumption is 2.3 mW and the achieved FoM is equal to 172.8 dB.

This paper describes the design method for highorder multi-bit incremental converters aiming at high resolution (> 14 bits) with Smart-DEM algorithm. Traditional 2ndand 3rd-order incremental ADCs use 1-bit quantizer. These structures lead to long conversion time for each sample to achieve the expected resolution and high power consumption due to the large output swing of the op-amps. Also, the fractional coefficients along the accumulation path that avoid instability degrade the performance. On the contrary, modulators employing multi-bit quantizer and DAC do not suffer from these problems. Although the mismatch of unity elements in the DAC causes non-linearity issue, this can be suppressed by Smart-DEM algorithm. Because the Smart-DEM algorithm is quite compact and easy to implement, the modulator benefits extra bits performance directly from the multi-bit DAC with affordable digital circuits overhead. In this paper several structures for incremental ADCs utilizing multi-bit quantizer are presented. The positive-and-negative DAC and the Smart-DEM algorithm are explained. With 3-bit quantizer, the simulation results show that the 2nd-order incremental ADC obtains 18-bit resolution with 256 clock periods.

This paper presents design and experimental results of a second-order, discrete-time, quadrature band-pass ΣΔ modulator targeted for wireless body area networks. The non-conventional architecture locks the intermediate frequency (IF) to the sampling frequency. Measurement results collected from a CMOS 0.18-μm prototype achieves a peak SNR of 55 dB over 100-kHz bandwidth and 40-dB SNR over 2.6-MHz bandwidth for a sampling frequency of 20 MHz with 1.96 mW power dissipation.

A second-order multi-bit hybrid continuous-time (CT) ΣΔ modulator has been implemented in a 65-nm CMOS technology. The circuit ensures jitter immunity granted by the use of multi-rate switched-capacitor (SC) DACs. An auxiliary digital assistance technique reduces integrators output swing. The modulator provides 10.8 bits of resolution over a signal bandwidth of 1.1 MHz and a spurious free dynamic range (SFDR) of 78 dB. The chip draws 1.1 mW from a 1-V supply.

This paper presents a new concept for an effective design of quadrature band-pass ΣΔ modulators with built-in Signal Transfer Function (STF) filtering action and discusses the architectural level implementation issues for second and third order modulators based on delay line topologies. The methodology uses an architecture which locks the intermediate frequency (IF) to the sampling frequency for both STF and Noise Transfer Function (NTF). Robustness of the structure against the mismatch is analyzed with interference tones placed in different locations of the receiver spectrum, including the image band. Simulations at the behavioral level verify the architecture implementation and the effectiveness of the approach.

An architecture for low-power ΔΣ modulators suitable for high-resolution portable sensor systems is presented. The circuit uses a single operational amplifier to achieve a third-order noise shaping. The two-stage op-amp employs a boosting technique that increases by 5 the slew-rate. The circuit, simulated at the transistor level using a conventional 0.18-μm CMOS technology, obtains a peak SNDR of 88 dB over an input signal bandwidth of 100 kHz. The simulated power consumption is 125 μW with a 1.5-V supply voltage. The achieved Figure of Merit (FoM) is 31 fJ/conversion-level.

This paper presents a new solution to obtain a spurs-free high precision amplifier. The method involves input chopping and correlated double sampling signal de-chopping. The offset is removed by using DC coupling. The proposed method, verified with transistor level simulations, is applied to a rail-to-rail input amplifier with 187 dB DC gain and 13.7 μA current consumption.

In this paper we present a MASH bandpass ΣΔ modulator for WCDMA applications. The signal bandwidth of the proposed modulator is 10 MHz, centered around an intermediate frequency (IF) of 70 MHz. Each ΣΔ modulator of the MASH structure is based on a two-path architecture, which allow us to obtain the desired in-band noise shaping zeros and reduce the power consumption. The ΣΔ modulator is implemented using a 0.18-nm CMOS technology and a sampling frequency of 180 MHz. The simulations at transistor level show a resolution of about 13 bits, with a bandwidth of 10 MHz, and a power consumption of about 90 mW, with a supply voltage of 1.8 V, resulting in a figure of merit (FoMBP) as low as about 0.15 pJ/conversion-level.

A fully digital feedforward ΣΔ modulator is described. The technique, here applied to a second order low-pass modulator, strongly reduces the operational amplifiers output swing, thus allowing the use of power effective single stage architectures. The method enables reduced slew-rate requirements and allows operation at lower power supply voltages. The proposed technique has better or comparable performance than more power hungry conventional analog and digital feedforward solutions. Behavioral simulations and a sensitivity analysis demonstrate the effectiveness of the approach.

A two stage op-amp with an effective technique to enhance slew-rate and gain is presented. The enhancement is provided by an auxiliary monitor circuit which is activated in slewing conditions, but can contribute to the gain in normal conditions. The amplifier, simulated in a 0.18 Omegam technology, achieves 74 dB DC gain, 160 MHz bandwidth and 26.8 V/mus slew-rate for a load capacitance of 1.75 pF with 362 muW power consumption, considering a supply voltage of 1.8 V.

Design strategies for power effective medium/high resolution Successive-Approximation ADC are discussed. The study considers reducing the power of the capacitive array with suitable capacitive attenuators that do not need using non-unity capacitors. The design of minimum power comparators is analyzed and a novel comparator scheme, named time-domain comparator, is described. The proposed methodologies, verified with a test design, is capable to provide 12-bit with 50-kHz signal band and 1-V supply. The achieved FoM is 14 fj/conv-level, which is well below the state-of-the-art.

Design techniques for single inductor multiple output (SIMO) DC-DC buck converters are presented. The suitable control of a multiple feedback loop enables the sharing of a single inductor with many outputs with a good stability and limited cross regulation. The method has been verified with simulations at the behavioural and transistor level to obtain four independent regulated output voltages ranging from 0 V to 1 V below the power supply voltage. The use of a suitable analog processing of errors allows obtaining a power efficiency as high as 86%.

The design strategies for band-pass SigmaDelta modulators are discussed. This paper studies two different approaches: the use of resonators and the synthesis of the noise transfer function (NTF) starting from a closer function. The use of a MASH configuration to obtain multiple zeros or splitting the complex zeros of the NTF is also discussed. The sensitivity to components mismatch of the proposed solutions is studied to identify advantages and limits of various presented architectures. Results show that mismatch errors in the fraction of percent range do not degrade the SNR significantly.

In recent years, continuous research efforts have been concentrating in increasing ΣΔ modulators operating frequency, while still reducing their power consumption. Indeed, when the ΣΔ modulator figure of merit (FoM) is less than 1 pJ/conversion, the decimation filter power consumption becomes a critical parameter. This paper presents a low power sin3FIR filter for ΣΔ modulators. The proposed filter implements a decimation by 4, operating at 64 MHz and consumes only 0.1 pJ/sample processed. The circuit has been implemented and simulated in a 0.18-μm CMOS technology, showing an overall power consumption reduction of about 67% with respect to a conventional design. Finally, a silicon area reduction of 17% in the combinatory part of the filter can also be achieved.

This paper presents a low-ripple voltage tripler charge-pump intended to provide a stable supply voltage to the cascaded circuits, thus allowing relaxed design specifications of the latter. The structure, which is implemented by means of an array of charge pump modules sequentially enabled, was developed for a phase-change memory (PCM) device, but it is also suitable for use in other applications. The circuit was integrated in a PCM test-chip, fabricated in 0.35-mum CMOS technology. An output voltage ripple of only 16 mV has been experimentally demonstrated

This paper presents a non-conventional program pulse approach for phase-change memories (PCMs). The cell programming curve is experimentally evaluated and discussed. The proposed set-sweep program pulse allows compensating for spreads in cell physical parameters. This ensures a better SET condition for marginal cells and adequately narrow SET distributions, which results in improved read margin. Experimental results have been collected from a 8-Mb BJT-selected PCM demonstrator. The effectiveness of the proposed program pulse has been proved by comparing cell distributions obtained on the whole array by means of a conventional SET box and a set-sweep program pulse, respectively.