Static random access memory (SRAM)-based ternary content addressable memory (TCAM) offers TCAM functionality by emulating it with SRAM. However, this emulation suffers from reduced memory efficiency while mapping the TCAM table on SRAM units. This is due to the limited capacity of the physical addresses in the SRAM unit. This brief offers a novel memory architecture called a resource-efficient SRAM-based TCAM (REST), which emulates TCAM functionality using optimal resources. The SRAM unit is divided into multiple virtual blocks to store the address information presented in the TCAM table. This approach virtually increases the overall address space of the SRAM unit, mapping a greater portion of the TCAM table in SRAM and increasing the overall emulated TCAM bits/SRAM at the cost of reduced throughput. A 72 × 28-bit REST consumes only one 36-kbit SRAM and a few distributed RAMs via implementation on a Xilinx Kintex-7 field-programmable gate array. It uses only 3.5% of the memory resources compared with a conventional SRAM-based TCAM (hybrid-partitioned TCAM).

Multiple cell upsets (MCUs) become more and more problematic as the size of technology reaches or goes below 65 nm. The percentage of MCUs is reported significantly larger than that of single cell upsets (SCUs) in 20 nm technology. In SRAM and DRAM, MCUs are tackled by incorporating single-error correcting double-error detecting (SEC-DED) code and interleaved data columns. However, in content-addressable memory (CAM), column interleaving is not practically possible. A novel error correction code (ECC) scheme is proposed in this paper that will cater for ever-increasing MCUs. This work demonstrated that m parity bits are sufficient to cater for up to m-bit MCUs, with an understanding of the physical grouping of MCUs. The results showed that the proposed scheme requires 85% fewer parity bits compared to traditional Hamming distance based schemes.

As transistor geometry shrinks, the erroneous and spurious charge from a particle strike tends to be shared by multiple nodes and causes multiple nodes upset. Such SEU mechanism invalidates the hardening principle of protecting a single node in relatively larger technologies. SEU needs to be accordingly understood and evaluated. In an 28-nm design example, SEU can happen in 6-day interval if no mitigation technique is used.

In this paper, we propose the use of ad-hoc scrubbing sequences to improve memory reliability. The key idea is to exploit the locality of the errors caused by a Multiple Cell Upset (MCU) to make scrubbing more efficient. The starting point is the MCU distributions for a given device. A procedure is presented that uses that information to determine an ad-hoc scrubbing sequence that maximizes reliability. The approach is then applied to a case study and results show a significant increase in the Mean Time To Failure (MTTF) compared with traditional scrubbing.

Reliability is a critical issue for memories. Radiation particles that hit the device can cause errors in some cells, which can lead to data corruption. To avoid this problem, memories are protected with per-word error correction codes (ECCs). Typically, single-error correction and double-error detection (SEC-DED) codes are used. As technology scales, errors caused by radiation particles on memories tend to affect more than one cell—what is known as a multiple cell upset (MCU). To ensure that only a single cell is affected in each word, interleaving is used. With interleaving, cells that belong to the same word are placed at a sufficient distance such that an MCU will only affect a single cell on each word. The use of interleaving significantly increases the cost of the device. Also, determining the interleaving distance (ID) required to avoid MCUs causing double errors is not trivial. Typically, accelerated radiation experiments with a limited number of particle hits are used. They provide a lower bound on the required ID, but larger MCUs may occur with a low probability. But even if the percentage of such large MCUs is very low, the impact on reliability can be significant. This article presents a technique to mitigate the effects of large MCUs that is, those that exceed the ID, on memory reliability. The proposed approach is able to correct most double errors caused by large MCUs by exploiting the locality of the errors within an MCU.

Testing for delay faults in heavily gated clock designs has the major test challenges of reduced fault coverage and high test power consumption. In the scan-test method, gated clocks are often simplified and replaced with global test clocks. As such, partial clocking by the gated clocks is not inherited in test operations. Global clocking suffers from delay fault coverage loss because a sensitization state cannot easily be created due to the increased state dependence in functional paths, as compared to partial clocking. The global clocking scheme in the test mode is not adequate for low-power designs either, because the power consumed during a test operation exceeds that used during a normal operation. The power grid may not be sufficient to support the power drawn during testing, perhaps resulting in overkilled devices. It is therefore critical that power consumption be maintained under a safe limit, even during testing. In the proposed method, partial clocking in gated designs is preserved to the maximum possible to create more reachable states, thereby increasing transition fault coverage and reducing test power during launch and capture cycles. A transition fault simulator was developed, and it demonstrated higher transition fault coverage and reduced test power for ISCAS-89 circuits when partial clocking is used.

This paper introduces effective test patterns for system-on-chip and board interconnects. Initially, “$6n$” patterns are introduced to completely detect and diagnose both static and crosstalk faults, where “$n$” is the total number of interconnect nets. Then, more economic “$4n + 1$” patterns are described to test the crosstalk faults for the interconnect nets separated within a certain distance.

This paper presents a novel input test buffer design methodology that is used for testing the differential signaling interconnects. The input test buffer is aimed to detect hardware failures in differential electrical connections. The input test buffer can also be used to check the differential signal's connectivity such as, diagnosing the cable connections, detecting off-lined or un-powered connections. The strategy employed here is to analyze the fault syndromes instead of enumerating the defects to achieve high fault coverage. This analysis leads to defining the key design components comprising of an analog null detector that detects and preserves the fault information in the signal, and several digital engines that process this signal. Preserving the fault information is crucial, as the differential input/output (I/Os) are robust enough to mask the defective signal. The functionality of the test buffer is clearly defined such that the user can customize it to a specific I/O technology. The impact on performance and area are negligible. The proposed input test buffer design was implemented and verified in designs using regular current mode logic (CML) differential input buffers in the 0.13-/spl mu/m process. The results demonstrate comprehensive coverage for catastrophic defects. The fault detection capability is demonstrated through Spice based fault simulations.

Presents the new technology that extends today's JTAG's capability from DC domain to both AC and DC domains. New concept, AC_EXTEST is introduced to support AC interconnection test and to have backward compatibility with EXTEST. It leverages existing application software available within the boundary-scan test industry to promote this technology to the manufacturing floor with minimal impact.

Clock line control (CLC) is proposed as a new design for testability technique which can transform a complex test generation problem into many small ones that are efficiently manageable by selectively enabling or disabling the synchronous operation of modules. A novel sequential test generation technique for the circuits with CLC scheme is also presented. The new test generation methodology is able to selectively clock modules, expand multiple time frames for a sequential module and compose these local time frames to generate input and clock vectors for an entire circuit. Test generation for the ISCAS'89 circuits, with and without CLC has been performed. Higher fault coverage in a shorter time has been achieved using test generation with CLC.

This paper presents a novel sequential test generation technique for circuits with clock line control (CLC). CLC is a design for testability (DFT) technique that can transform a complex test generation problem into multiple small ones that are efficiently manageable by selectively enabling or disabling the synchronous operation of modules. The new test generation methodology for CLC circuits is smart enough to selectively clock modules, expand multiple time frames for a sequential module and compose these time frames to generate input and clock vectors for an entire circuit. Test generation for the ISCAS '89 circuits, with and without both CLC and scan has been performed. High fault coverage in a short time has been achieved using test generator with CLC.>

A hybrid DFT method is proposed to reduce the hardware penalty of traditional DFT methods and test generation time. It takes advantages of both traditional DFT methods like scan and DFT methods which control clocks for testability. The hardware scheme and test generation algorithm are presented. Test generation results for ISCAS '89 circuits have been generated and showed an improvement in test generation time and fault coverage.