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Hemant Mahawar

dblp:75/4509 · DBLP profile ↗
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5ranked-venue papers
5as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 5 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% Integrated circuit design · 9%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › interconnect modeling
inductance extraction
0.012002
A solenoidal basis method for efficient inductance extraction · DAC 2002
Electronic design automation › physical design › parasitic extraction
interconnect parasitic extraction
0.012002
A solenoidal basis method for efficient inductance extraction · DAC 2002
Electronic design automation
physical design
0.012002
A solenoidal basis method for efficient inductance extraction · DAC 2002

Methods — techniques the papers use, named apart from their topics

solenoidal basis method · 0.0preconditioning · 0.0GMRES · 0.0
YearPublicationVenuePosition
2006 Parallel algorithms for inductance extraction of VLSI circuits
abstract
Inductance extraction involves estimating the mutual inductance in a VLSI circuit. Due to increasing clock speed and diminishing feature sizes of modern VLSI circuits, the effects of inductance are increasingly felt during the testing and verification stages. Hence, there is a need for fast and accurate inductance extraction software. A generalized approach for inductance extraction requires the solution of a dense complex symmetric linear system that models mutual inductive effects among circuit elements. Iterative methods are used to solve the system without explicit computation of the matrix itself. Fast hierarchical techniques are used to compute approximate matrix-vector products with the dense system matrix. This work presents an overview of a new parallel software package for inductance extraction of large VLSI circuits. The technique uses a combination of the solenoidal basis method and effective preconditioning schemes to solve the linear system. Fast multipole method (FMM) is used to compute approximate matrix-vector products with the inductance matrix. By formulating the pre-conditioner as a dense matrix similar to the coefficient matrix, we are able to use FMM for the preconditioning step as well. A two-tier parallelization scheme allows an efficient parallel implementation using both OpenMP and MPI directives simultaneously. The experiments conducted on various multiprocessor machines demonstrate the portability and parallel performance of the software.
Hemant Mahawar, Vivek Sarin
IPDPS1
2004 Parallel Performance of Hierarchical Multipole Algorithms for Inductance Extraction
Hemant Mahawar, Vivek Sarin, Ananth Grama
HiPC1
2004 Parallel Software for Inductance Extraction
abstract
The next generation VLSI circuits will be designed with millions of densely packed interconnect segments on a single chip. Inductive effects between these segments begin to dominate signal delay as the clock frequency is increased. Modern parasitic extraction tools to estimate the onchip inductive effects with high accuracy have had limited impact due to large computational and storage requirements. This work describes a parallel software package for inductance extraction called ParIS, which is capable of analyzing interconnect configurations involving several conductors within reasonable time. The main component of the software is a novel preconditioned iterative method that is used to solve a dense complex linear system of equations. The linear system represents the inductive coupling between filaments that are used to discretize the conductors. A variant of the fast multipole method is used to compute dense matrix-vector products with the coefficient matrix. ParIS uses a two-tier parallel formulation that allows mixed mode parallelization using both MPIand OpenMP. An MPI process is associated with each conductor. The computation within a conductor is parallelized using OpenMP. The parallel efficiency and scalability of the software is demonstrated through experiments on the IBM p690 and Intel and AMD Linux clusters. These experiments highlight the portability and efficiency of the software on multiprocessors with shared, distributed, and distributed-shared memory architectures.
Hemant Mahawar, Vivek Sarin
ICPP1
2003 Parallel iterative methods for dense linear systems in inductance extraction
Hemant Mahawar, Vivek Sarin
Parallel Comput.1
2002 A solenoidal basis method for efficient inductance extraction
abstract
The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction is the solution of large, dense, complex linear systems of equations via iterative methods. Accelerating the convergence of the iterative method through preconditioning is made difficult due to the non-availability of the system matrix. This paper presents a novel algorithm to solve these linear systems by restricting current to a discrete solenoidal subspace in which Kirchoff's law is obeyed, and solving a reduced system via an iterative method such as GMRES. A preconditioner based on the Green's function is used to achieve near-optimal convergence rates in several cases. Experiments on a number of benchmark problems illustrate the advantages of the proposed method over FastHenry.
Hemant Mahawar, Vivek Sarin, Weiping Shi
DAC1