Recent advances in CMOS technology have enabled the implementation of high-performance and energy-efficient digital-intensive radio transceivers for fifth-generation (5G) and beyond (6G) wireless communication systems. Among the various transmitter architectures, the outphasing transmitter with constant-amplitude modulation, which allows the use of highly energy-efficient nonlinear power amplifiers, has garnered significant attention since it easily lends itself to a digital-intensive implementation, thus fully exploiting the benefits of scaled CMOS technologies. However, an outphasing transmitter with a delay-based phase modulator suffers from performance degradation due to mismatch-induced static nonlinearity. This paper presents a linearization algorithm that minimizes mismatch-induced static nonlinearity by reordering the unary-weighted delay elements. The effectiveness of this algorithm is demonstrated through simulations and its application to measured delay characteristics from a 22-nm FDSOI CMOS transmitter prototype in a system simulation. The proposed reordering algorithm results in a 7.94% points improvement from 10.63% in EVM and a 7.76dB enhancement from 25dB in ACLR for a 5G NR 64-QAM OFDM waveform with a 200MHz bandwidth.

This paper analyses and compares key differences between active and passive mixer structures in the context of mmWave applications. Firstly, the paper analyses mixer switching stage input impedance and its implications on frequency response. Active mixers provide isolation, whereas passive switching entails impedance transparency beneficial for filtering. Secondly, the paper analyses mixer performance with a low-amplitude sinusoidal LO signal typical for mmWave frequencies. Such an LO signal entails partly overlapping, unideal switching. However, active switching transistors commutate current more ideally during the overlap stage, demonstrating superior sinusoidal LO signal tolerance. Importantly, this work demonstrates that despite multiple passive mixer benefits, their performance is highly dependent on the LO signal. Finally, based on the analysis, the paper introduces a wideband active mmWave downconversion mixer design in 22-nm FDSOI CMOS. Measured characteristics demonstrate a particularly wide bandwidth of 55 to 100 GHz.

Time-based analog-to-digital converters (ADCs) have recently gained attention because of their ability to reach high sample rates with good energy efficiency. The performance of most implementations is limited by the Voltage-to-Time Converter (VTC), hence necessitating thorough analysis on its performance. This paper derives expressions for the noise and linearity of a constant-slope VTC. The derived expressions provide an explicit link between the circuit parameters and VTC performance as well as offer insight on the available trade-offs. Based on the expressions, a general design methodology for constant-slope VTCs is proposed. The simulated verification with 28-nm CMOS shows good agreement with the presented analysis and with previously measured results, thereby corroborating the proposed design methodology. The presented design methodology allows the developed understanding between the VTC circuit parameters and performance metrics to be utilized in e.g. design exploration and algorithmic circuit optimization to find an optimal set of parameters for a given target specification.

The digital front-end of the communication transceivers envisioned for fifth-generation (5G) and beyond requires highly configurable high-performance digital signal processing (DSP) hardware operating at very high sampling rates to accommodate increasing signal bandwidths and support a range of modulation schemes and transmitter architectures. In this article, we present an efficient implementation of a highly configurable DSP hardware generator that can generate high-performance DSP hardware for multiple transmitter architectures including Cartesian, polar, outphasing, and multilevel outphasing modulators. The generated hardware unit, which consists of multistage multirate filters and other required DSP operations, runs at sample rates up to 4 GHz. The hardware supports an adjacent channel leakage ratio (ACLR) down to −48 dB and an error vector magnitude (EVM) of 0.78% with a 7-bit phase signal at a sampling rate of 4 GHz for multilevel outphasing modulation. Digital synthesis of the circuit in a 5-nm complimentary metal-oxide semiconductor (CMOS) process yields a core area consumption of 0.01 mm2 and an estimated power consumption of 37.2 mW for a 200-MHz bandwidth 5G new radio (NR) baseband (BB) signal.

This article presents a wideband active millimeter wave (mmWave) CMOS downconversion mixer preceded by thorough analysis. This article aims to provide solid reasoning for the proper choice of mixer topology and present methods to achieve high mixer performance, guiding mmWave mixer design. The article first analyses passive and active mixer input impedance and switching performance with a weak sinusoidal local oscillator (LO) signal, demonstrating that passive mixer switching performance is far more dependent on the LO signal. The article then introduces different active mixer design enhancement techniques, namely, peaking inductances and individual mixer stage biasing. The article proposes an enhanced Gilbert cell mixer that uses transformer coupling between the transconductance and switching stages. The complete mixer structure with an LO buffer and an IF amplifier consumes an area of only 0.13 mm2 fabricated in a 22-nm FDSOI process. The design achieves a measured peak voltage conversion gain (CG) of 3.5 dB, an exceptionally wide 55–100-GHz RF bandwidth, and a 10-GHz IF bandwidth. The complete mixer consumes 33 mW of power from a low 0.8-V supply voltage and demonstrates an input 1-dB gain compression point of −6 dBm.

Cyclic-coupled ring oscillators (CCRO), which consist of M ring oscillators each with N inverting stages, can be used in time-domain data converters to achieve sub-gate-delay resolution and improved phase noise performance compared to a single ring oscillator (RO). However, CCROs can oscillate in several different oscillation modes, where some modes contain overlapping phases. Such in-phase oscillations severely degrade the performance of a time-domain data converter by undermining the sub-gate-delay of the CCRO. This paper presents a design method to avoid the undesired in-phase oscillation modes, and thus achieve guaranteed maximal phase resolution regardless of the oscillation mode, by properly selecting the CCRO dimensions N and M. We show, both theoretically and with transistor-level simulations, that mode-agnostic maximum phase resolution can be ensured by selecting a prime M together with an N which is co-prime with M.

Time-interleaved analog-to-digital converters (TIADC) require channel matching in terms of offset, gain, and sampling clock skew to achieve best data conversion performance. Conventionally, correction of skew mismatch is realized with analog delay lines, making it challenging for high-speed ADC designs to achieve fine delay resolution over wide tuning range while maintaining low clock jitter. Digital skew correction allows greater flexibility than analog solutions, but is hindered by a significant hardware footprint. This paper demonstrates digital filter-based timing skew correction approach suitable for on-chip implementation. In a 10-bit 8-channel TI-ADC the proposed structure corrects mismatch magnitudes up to 0.12 sample period across 0.9 Nyquist band while requiring only 65% hardware of similar architectures of equivalent performance. The presented digital circuit uses reduced combinational paths and operates at a clock rate of single ADC channel, making it applicable for digitally-assisted high-speed TI-ADCs.

This paper describes the design and post-layout simulations of a 2/3/4- modulus frequency divider circuit, accompanied with an accumulator that controls the division count. The circuit is capable of operating as an integer or as a fractional divider. Key topic of this paper is the merging of div-2/3 and div-3/4 circuits into a single compact circuit that solves an issue of a forbidden state in fractional-division operation. The circuit is designed with 28-nm CMOS technology and the post-layout simulations indicate an operating input frequency range of 0.3 - 5.4 GHz with 13-bit fractional frequency resolution between division ratios of 2-4. The divider occupies only 40 pm × 30 pm while consuming 2.0 mW at 5.4 GHz input frequency.

This paper describes the design of a 140-GHz low- noise amplifier in 130-nm SiGe BiCMOS technology. The circuit is aimed for a high integration-density imaging radiometer, where several receivers are integrated on the same die. Thus, we particularly focus on minimizing the die area and power consumption. The two-stage amplifier is composed of cascode stages with gain boosting base resonators. The performance of a single cascode stage is optimized by correctly sizing the base resonator to avoid instability and optimizing the compact transistor layout without typically used interstage matching between the cascode stages. The circuit features gain of 19 dB at 140 GHz, and noise figure of 7 dB, while consuming only 15 mW with the supply voltage of 2 V and occupying a die area of 0.1 mm2.

An integrated circuit that measures time intervals with high precision and accuracy has a wide range of applications including data conversion, ranging, and 3-D imaging. The resolution with which time intervals are quantized by a ring oscillator or delay line is limited by the minimum delay of an inverter in the technology. We propose the use of cyclic-coupled ring oscillators (CCROs) as a time-domain quantizer to achieve a combination of subgate-delay time resolution together with a short conversion time, thereby enabling data conversion with high resolution as well as high bandwidth. The resolution-power tradeoff in coupled oscillators is studied. Simulation indicates up to a factor-of-13 subgate-delay time resolution with 13 coupled oscillators. A real-time quantizing time-to-digital converter with coupled oscillators is designed for a time-domain analog-to-digital converter. Powered by a factor-of-8 subgate-delay time resolution of 1.6 ps obtained with nine coupled oscillators, and a sample time of 4 ns for 11-bit conversion, the converter delivers a 9.9-bit ENOB over a signal bandwidth of 125 MHz and an SFDR of 88 dB. Results demonstrate that CCROs is an attractive candidate as a high-precision high-linearity time-domain quantizer for data converters.

This paper describes the design and measurement of an open-loop fractional frequency divider implementation. The fractional divider consists of a multi-modulus integer frequency divider (MMD), a sigma-delta modulator (SDM) and a pipelined phase interpolator. The fractional frequency division is achieved with the MMD and the 13-bit SDM toggling the integer division ratio. The resulting signal is then processed by the phase interpolator which significantly reduces the spurs by 22 dB and generates spectrally clean signal with correct output frequency. The prototype is implemented in 28-nm CMOS technology and it operates within input frequency range of 1.9 GHz - 3.5 GHz with fractional division ratio in between 2-3. As an example of the operation, with a setting of an arbitrary division ratio of 2.3164 and input frequency of 2.4 GHz, the output sets correctly to 1.0361 GHz with RMS jitter of 2.1 ps.

In this paper we propose two methods to boost the power supply rejection (PSR) of an output-capacitor-less low-dropout regulator (LDO). Our LDO is targeted for low-power system-on-chip applications, such as medical electronics, RFIDs, and IoT devices, where applied energy harvesting techniques induce large voltage ripple to supply line, thus requiring high PSR out of the LDO. The regulator utilizes a feed-forward path through the amplifier power supply rail to pass-transistor gate. Furthermore it includes a feed-forward amplifier to improve the frequency response and a feedback amplifier to stabilize the LDO, eliminating the need for an area consuming compensation capacitor. The proposed LDO is implemented in 28-nm CMOS technology. It supplies 700-mV output level with a current range of 0-5 mA and a 100-mV dropout voltage. The three amplifiers within our LDO consume only a total of 13 μA, thus regardless of increased complexity, high current efficiency of 99.74% is maintained. At the nominal load of 1 mA, low-frequency PSR reaches a value of -97 dB and at the high-frequency range of 1- 20 MHz PSR is boosted to remain below -20 dB and the region of 3-10 MHz below -30 dB.

A digital-friendly approach to implement injection-locked ring oscillators is proposed. We show that lock can be achieved by dynamically switching the delay of a delay element in a ring oscillator. A logic gate that generates the control signal for switching the delay, together with a one-bit controlled oscillator, inherently realizes a locking mechanism. Measurement results from a prototype circuit fabricated with a 28 nm CMOS process demonstrate the feasibility of the concept. The circuit with a measured lock range of 2.4-3.7 GHz occupies an area of 0.00043 mm2and consumes 0.18 mW power.

Full-Duplex (FD) transceiver architectures have recently gained increased attention due to their potential for doubling the theoretical spectral efficiency. One of the main challenges in FD transceivers is the self-interference (SI) from the local transmitter (TX). In this paper we present a novel analog SI cancellation technique through buried-gate signaling in the fully-depleted silicon-on-insulator (FD-SOI) process. The proposed technique attenuates the TX leakage in the receiver (RX) chain before gain is applied. This relaxes the dynamic range requirement of the later RX stages by the amount of attenuation offered by the buried-gate signaling. Further, in comparison to other published analog techniques, the proposed technique offers no penalty on RX noise figure. Measured results in a 28nm FD-SOI technology demonstrate 40-50dB of SI cancellation for TX leakage as high as -10dBm, and above 20dB for TX leakage of -5dBm, with no increase in the RX noise figure.

This paper describes implementation details of a digital-intensive phase modulator architecture that does not require a frequency synthesizer to cover a wide carrier frequency range. The phase modulator operation is based on toggling the output accurately during the sample period to generate the phase-modulated signal. The toggling instants within the sample period are calculated by DSP solvers that utilize linear interpolation. The interpolation effectively multiplies the phase signal sample rate by the modulator phase resolution, which enables wider signal bandwidth and a completely digital method of defining the transmitter carrier frequency. The phase modulator concept is verified by implementing it as a part of an outphasing transmitter in 28 nm CMOS. With a constant sample rate of 1.5 GHz and without any predistortion, the transmitter achieves better than -28 dBc ACLR with 100 MHz aggregated LTE downlink signal between 0.8-2.0 GHz carrier frequency.

This paper examines one source of spectral degradation in polar and multilevel outphasing transmitters. The degradation is caused by the amplitude signal appearing at the transmitter output as a baseband component, in addition to the desired RF signal. This baseband component contains sampling images and quantization noise across the spectrum. Thus, it adds noise at the signal band where it cannot be filtered and limits the achievable ACLR, particularly in wideband LTE and 5G systems. We analyze the origin of this phenomenon and related effects of system and signal parameters, and propose three design solutions for eliminating or alleviating the problem. Our analysis and simulations demonstrate that using a voltage-subtracting power combiner cancels the described degradation, potentially leading to significant improvement in spectral performance.

This paper proposes a new type of delay line locking mechanism with digitally controlled charge transfer. Delay-locked loop (DLL) based on the presented method features multi-phase outputs and is stepwise driven towards lock by a co-action of 1-bit Time-to-Digital Converters and revised charge-pump. On-chip pulse “slicing” arrangement provides high-rate clock for the Digital Signal Processing algorithm, enabling fine-tuninig of the proposed DLL. Locking mechanism is implemented with standard digital cells and complete mixed-signal design is simulated in 28nm ST CMOS with full physical device models to prove functionality. When locked to reference frequency of 1.25GHz, this design consumes 1.1mW from 1V supply and produces 64+64 12ps-spaced output phases with <;176fspp phase error ripple and 50dB SFDR.

This paper presents a wideband blocker-tolerant Direct ΔΣ receiver (DDSR). Blockers are attenuated through selective input impedance matching and optimized gain design. The created impedance profile provides low receiver input impedance at blocker frequencies, while at desired frequencies, the impedance is boosted to matched condition through an up-converted positive feedback from the DDSR output. Receiver is evaluated in a 28nm fully-depleted silicon-on-insulator CMOS process with total power consumption of 25mW at 1V supply voltage. The receiver is designed for configurable operation from 0.7-2.7GHz, a baseband bandwidth of 10MHz, demonstrates a maximum noise figure of 6.2dB, and achieves a peak SNDR of 53dB with an out-of-band 1dB input compression point of -11.5dBm at 100MHz offset.

In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.

This paper presents a clock generator for a MIPI M-PHY serial link transmitter, which includes an ADPLL, a digitally controlled oscillator (DCO), a programmable multiplier, and the actual serial driver. The paper focuses on the design of a DCO and how to enhance the frequency resolution to diminish the quantization noise introduced by the frequency discretization. As a result, a 17-kHz DCO frequency tuning resolution is demonstrated. Furthermore, implementation details of a low-power programmable 1-to-2-or-4 frequency multiplier are elaborated. The design has been implemented in a 40-nm CMOS process. The measurement results verify that the circuit provides the MIPI clock data rates from 1.248 GHz to 5.83 GHz. The DCO and multiplier unit dissipates a maximum of 3.9 mW from a 1.1 V supply and covers a small die area of 0.012 mm2.

This paper presents two all-digital RF frequency synthesizers implemented in 65-nm CMOS: a digital period frequency synthesizer and an all-digital phase-locked loop. This paper is especially focused on the implementation issues and practical challenges of digital frequency synthesizers for wideband radio systems. Moreover, the paper presents implementations and experimental results of these two frequency synthesizers targeted for cognitive radio spectrum sensing applications.

A wideband receiver for cognitive radio spectrum sensing unit is presented. The circuit consists of a high-linearity low-noise amplifier, passive mixer, and base-band buffer. IQ signals for the LO are generated using a divide-by-two circuit. Low-noise amplifier includes common-gate common-source combination for simultaneous interference suppression and noise canceling. The receiver operates in the LTE bands at 0.7 - 2.6 GHz, with measured performance of 31-dB gain, 11-dB noise figure, and 2-dBm IIP3 linearity. The circuit is fabricated in 65 nm CMOS technology and it occupies 0.3-mm2active area.

This paper presents an analysis and design of a digitally controlled ring oscillator with a new band-extension technique to achieve wide-band operation. The proposed technique is based on inclusion of an LC tank to boost the frequency range. Two frequency sub-ranges are covered with the tank on and off respectively, and they jointly constitute a very wide frequency tuning range. Implemented as a building block of a digital frequency synthesizer, the ring oscillator has a measured tuning range of 2.65-6.3 GHz, with power consumption less than 16 mW from a 1.2-V supply. The worst-case measured phase noise at 1-MHz offset is -85 dBc/Hz.

Integrated active inductor configurations for RF frequencies are examined in this paper. A new aspect of comparing the performance of different topologies is used, and consequent differences between technologies are recognised. On the basis of these studies a new method for raising the Q-factor is presented and its applications considered.>