The design of compact noise detector circuitry that could be embedded and arrayed within a high-density large-scale digital circuit was demonstrated. In-depth characterization of dynamic power-supply and ground noises by the built-in noise detection technique can validate and/or calibrate dynamic power-supply analysis (IR drop) methodologies that are becoming requisite to nanometer scale digital integrated circuits.

No abstract available.

The objective of this embedded tutorial is to give an overview for the state of the art of the pass-transistor logic technologies and their future prospects. The paper gives a survey summary for recent researches and developments on the pass-transistor logic technologies based on more than 100 surveyed papers that have been published after 1983. The number of publications has been rapidly increased after 1995, which shows recent quick growth of research activities. The survey includes several different viewpoints, such as circuit technologies, design and synthesis methodologies, applications and commercial use, etc. The circuit technologies and synthesis methodologies are roughly grouped into two categories, one of which has a close relation to BDD, while the other does not. Circuit technologies are also categorized into different axes, such as differential structure or single-rail structure, NMOS pass-transistors or CMOS, static circuits or dynamic, etc. Features of each pass-transistor logic family are explained along with these classification axes. For the most recent topics, commercial products by Japanese companies and cell/tool businesses in venture business companies in US are also reported. Several recent papers made performance comparisons of pass-transistor logic and CMOS, that are also reported with a discussion of future prospects.

A very low power 8-bit CPU core has been designed based on an original pass-transistor logic family, the SPL (single-rail pass-transistor logic) and SPHL (single-rail pass-transistor and holders logic). The instruction set and external timings are compatible with the Zilog Z80. The average supply current is 740 /spl mu/A at 3 V with a 10 MHz-clock, equivalent to 26% of that of the commercial CMOS Z80 CPU cores using the same design rules.

This paper presents a method of test generation for stuck-on faults in a pass-transistor logic SPL by logic testing. We describe how to create a discrepancy using a pre-computed table for voltage calculation. For solving a table explosion problem we present some techniques for extending the applicable scope of a restricted table in practical size. Then, we propose a simple DFT circuit. The experimental results show the effectiveness.

Good load balancing is the key to deriving maximal performance from multiprocessors. Several successful dynamic load balancing techniques on tightly-coupled multiprocessors have been developed. However, load balancing is more difficult on loosely-coupled multiprocessors because inter-processor communication overheads cost more. Dynamic load balancing techniques have been employed in a few programs on loosely-coupled multiprocessors, but they are tightly built into the particular programs and not much attention is paid to scalability. We have developed a dynamic load balancing scheme which is applicable to OR-parallel programs in general. Processors are grouped, and work loads of groups and processors are balanced hierarchically. Moreover, it is scalable to any number of processors because of this multi-level hierarchical structure. The scheme is tested for the all-solution exhaustive search Pentomino program on the mesh-connected loosely-coupled multiprocessor Multi-PSI, and speedups of 28.4 times with 32 processors and 50 times with 64 processors have been attained.

We evaluated a Prolog machine PSI (Personal Sequential Inference machine) for the purpose of improving and redesigning it. In this evaluation, we measured the execution speed and the dynamic characteristics of cache memory, register file, and branching hardware introduced for high-speed execution of Prolog programs.Execution speed of the PSI firmware interpreter was found to be comparable to that of the DEC-10 Prolog compiled code on the DEC-2060. It was also found that PSI was faster than DEC for executing programs containing much unification and backtracking that require runtime processing.With the cache memory, the hit ratio for application programs was found higher than 96%; this demonstrates that the Prolog execution has much memory access locality. The memory access frequency and the appearance ratio between Read and Write command were also investigated.Concerning the register file, use rate of each dedicated access mode was measured and effect of each mode was discussed. In the branching function we confirmed a high appearance rate of conditional branches and multi-way branches based on tag values.