Monolithic 3D (M3D) integration provides massive vertical integration through the use of nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-layer dielectric make ILVs especially prone to defects. We present a low-cost built-in self-test (BIST) method that requires only two test patterns to detect opens, stuck-at faults, and bridging faults (shorts) in ILVs. We also propose an extended BIST architecture for fault detection, called Dual-BIST, to guarantee zero ILV fault masking due to single BIST faults and negligible ILV fault masking due to multiple BIST faults. We analyze the impact of coupling between adjacent ILVs arranged in a 1D array in block-level partitioned designs. Based on this analysis, we present a novel test architecture called Shared-BIST with the added functionality of localizing single and multiple faults, including coupling-induced faults. We introduce a systematic clustering-based method for designing and integrating a delay bank with the Shared-BIST architecture for testing small-delay defects in ILVs with minimal yield loss. Simulation results for four two-tier M3D benchmark designs highlight the effectiveness of the proposed BIST framework.

Monolithic 3-D (M3D) integration has the potential to achieve significantly higher device density compared to 3-D integration based on through-silicon vias. We propose a test solution for M3D ICs based on dedicated test layers, which are inserted between functional layers. We evaluate the cost associated with the proposed design-for-test (DfT) solution and compare it with that for a potential DfT solution based on the IEEE Std. P1838. Our results show that the proposed DfT solution is more cost-efficient than the P1838-based DfT solution for a wide range of interlayer via density. We also present a test scheduling and optimization technique for wafer-level testing of M3D ICs. The proposed technique provides test schedules with minimum test time under power consumption and probe pad constraints.

Monolithic three-dimensional (M3D) integration has the potential to achieve significantly higher device density compared to 3D integration based on through-silicon vias (TSVs). We propose a test solution for M3D ICs based on dedicated test layers that are inserted between functional layers. We evaluate the cost associated with the proposed design-for-test (DfT) solution and compare it with that for a potential DfT solution based on the IEEE Std. P1838. Our results show that the proposed solution is more cost-efficient than the P1838-based solution for a wide range of inter-layer via (ILV) density, ILV yield, and defect density.

In this paper the design of a novel IP for 3D IC die-to-die clock synchronization is presented. The proposed design offers notable benefits over the conventional dual DLL based architectures for 3D IC clock synchronization. Simulation results of the IP are presented with GLOBALFOUNDRIES 14nm finFET library, and Through-Silicon Via (TSV) technology.

Monolithic three-dimensional (M3D) integration is gaining momentum, as it has the potential to achieve significantly higher device density compared to 3D integration based on through-silicon vias. M3D integration uses several techniques that are not used in the fabrication of conventional integrated circuits (ICs). Therefore, a detailed analysis of the M3D fabrication process is required to understand the impact of defects that are likely to occur during chip fabrication. In this article, we first analyze electrostatic coupling in M3D ICs, which arises due to the aggressive scaling of the interlayer dielectric (ILD) thickness. We then analyze defects that arise due to voids created during wafer bonding, a key step in most M3D fabrication processes. We quantify the impact of these defects on the threshold voltage of a top-layer transistor in an M3D IC. We also show that wafer-bonding defects can lead to a change in the resistance of interlayer vias (ILVs), and in some cases lead to an open in an ILV or a short between two ILVs. We then analyze the impact of these defects on path delays using HSpice simulations. We study their impact on the effectiveness of delay-test patterns for multiple instances of IWLS 2005 benchmarks in which these defects were randomly injected. Our results show that the timing characteristics of an M3D IC can be significantly altered due to coupling and wafer-bonding defects if the thickness of its ILD is less than 100nm. Therefore, for such M3D ICs, test-generation methods must be enhanced to take M3D fabrication defects into account.

Speed binning of system-on-chips (SoCs) using conventional Fmax test requires application of complex functional test patterns. Functional workload-based speed binning techniques incur high test-cost in terms of long test-time and complexity in functional test generation, and require high-end automatic test equipment. In this paper, we propose a novel speed binning flow that uses path timing slacks, extracted with robust digital embedded sensor IPs, of selected critical/nearcritical paths. We apply machine learning techniques to model a predictor considering the extracted slacks and the Fmaxvalues from a set of randomly tested die during wafer sort. The trained predictor is used to obtain the Fmaxfor the remaining chips. The proposed flow has been demonstrated in an SoC benchmark circuit at 28 nm technology. For sufficient number of training samples, Fmaxis correctly predicted for 99% of the prediction samples.

In interposer-based 2.5-D integrated circuits, the passive silicon interposer is the least expensive component in the chip. Thus, it is desirable to test the interposer before bonding to ensure that more expensive and defect-free dies are not stacked on a faulty interposer. We present an efficient method to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing. We present HSPICE simulation results to demonstrate the effectiveness of the prebond test solution. Test-path designs are also presented to highlight the efficiency of the test-path design algorithm. The benefit of using weighted critical area is demonstrated using a commercial interposer from industry.

In 3D packages top-die power delivery is a not only limited by back-end of line (technology scaling), but also by the TSV integration scheme, the stacking method and the microbump current-carrying capability. The microbump structure and its electromigration time-to-failure (TTF) rate determine the current carrying capability of each TSV, and this is far lower than the current-carrying capability of a C4 bump. Therefore, the power delivery to the top die(s) needs to be distributed through a network of TSVs that tie into the power grid of the top die. The drawback of such a design is the resistive losses in the BEOL of the bottom-die. In this paper, we highlight these challenges faced by each stacking method, and as a promising solution, we will present the use of a voltage-compensation network with dynamic IR-drop sensors that can be used as part of the power-delivery cell to maintain nominal power delivery during all loading cycles. This can help eliminate the use of off-chip voltage regulator modules.

This paper presents a hybrid electrical model of Carbon nanotube (CNT) based Through Silicon Via (TSV) using Metal Oxide Semiconductor (MOS) structural approach which takes into account factors such as substrate doping, operational frequency and voltage transmission levels. The MOS structural approach considers the CNT-based TSVs as a metal-oxide-semiconductor device, thereby resulting in a depletion capacitance which reduces the overall TSV capacitance. This affects the electrical performance of CNT-based TSVs, but has been ignored in previous models. Evaluation of electrical performance has been performed through S-parameter simulation of TSV and the simulation results have been compared with previously published electrical models of CNT-based TSV. The proposed hybrid electrical model shows CNT-based TSV better performance when compared with other published models.

Rapidly growing complexity in 3D ICs has led an increase in popularity of test methodologies based on delay testing. In this paper, we analyze the physical level design of 3-D stacked DRAM ICs with Through Silicon Via (TSV) to evaluate the propagation delay. We have performed design and electrical circuit model extraction to analyze the propagation delay in 3D DRAM ICs using the traditional 3-transistor model with 0.35nm CMOS technology. Simulation results are presented to show the accuracy and efficiency in determining the propagation delay in 3D DRAM ICs using the electrical circuit model proposed in this paper. We represent the propagation delay in TSVs by representing the RC time constant and the capacitive delay in DRAM cell load driver during pull up and pull down in CMOS. We have performed TDR and eye diagram analysis to validate our models. The proposed propagation delay model can be used for various high speed, high density memory.

This paper presents modeling and characterization of CNT-based TSVs for high frequency applications. We have developed an integrated model of CNT-based TSVs by incorporating quantum confinement effects of CNTs along with kinetic inductance phenomenon at high frequencies. Substrate parasitics have been appropriately modeled as monolithic microwave capacitor by resonant line technique using a two-polynomial equation. Different parametric variations in the model have been outlined as case studies. Furthermore, electrical performance and signal integrity analysis on different cases have been used to determine optimized configuration for TSV-based CNTs for radar applications.

This paper provides development of an RF circuit software tool that generates diagnostic programs automatically for device interface boards. The diagnostic tool utilizes novel techniques to differentiate faulty RF circuits embedded in printed circuit boards. The diagnostic tool provides user-transparent pseudocodes with high fault coverage and significantly decreases time to market.

This paper describes a low cost test technique for testing Analog-Mixed Signal and RF load boards used in ATE (Automatic Test Equipment). The paper describes the development and application of a software tool for automatic analysis and test generation for mixed signal and RF circuits on Device Interface Boards (DIB). DIBs are essential components for testing ICs and they contain mixed-signal and RF circuits with several active and passive components that are needed to simulate test conditions for ICs. The software tool utilizes the schematic information of DIBs to generate tests for components and interconnectivity on the DIB. The tests generated are dependent upon the accessibility and programmability provided by the test hardware as well as the testability provided by DIB design. The output of the tool is a generic test specification that is independent of test hardware platform. Automatic test generation saves on the manual labor for writing DIB tests and thus contributing to the reduction of time to market for ICs.