This paper addresses the challenges of minimizing the time and resources required to validate the changes between two Hardware (HW) model iterations of the same design. It introduces CLTV (Coverage Learned Targeted Validation), an automatic framework which learns during the verification process of the HW and uses the learned information to target the areas of the design that are affected by the incremental HW model iterations.

Dynamic BDD reordering is usually a computationally-demanding process, and may slow down BDD-based applications. We propose a novel algorithm for distributing this process over a number of computers, improving both reordering time and application time. Our algorithm is based on Rudell's popular sifting algorithm, and takes advantage of a few empirical observations we make regarding Rudell's algorithm. Experimental results show the efficiency and scalability of our approach, when applied within an industrial model checker.