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D. Mackay

dblp:76/1222 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 1 heaviest of 1, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › CAD framework
integrated circuit design system		 0.011981
CELTIC - solving the problems of LSI design with an integrated polycell DA system · DAC 1981
YearPublicationVenuePosition
2010 Easing the verification bottleneck using high level synthesis
abstract
As design size grows, the verification complexity grows along with the size of the design description. When design descriptions are written in RTL, the complexity of the testbenches to test this RTL are enormous. As more and more design entry moves to higher level languages such as C/C++ and System C, it's possible to write testbenches in C to verify the functionality of these high level models.
D. Varma, D. Mackay, P. Thiruchelvam
 VTS2
1981 CELTIC - solving the problems of LSI design with an integrated polycell DA system
G. Martin, J. Berrie, T. Little, D. Mackay, J. McVean, D. Tomsett, L. Weston
 DAC4