Network coverage is an increasing concern for the Quality of Service (QoS) targets of new mobile technologies. New solutions designed to fulfill the requirements of the existing fifthgeneration (5G) and upcoming sixth-generation (6G) emerging scenarios are based on deploying a high number of network access points (APs), which tend to considerably degrade coverage and cell-edge performance due to added interference and increase the energy consumption of cellular systems. In this paper, we present new results on our recently proposed novel concept of cell-sweeping that aims to minimize the coverage dead-spots and improve cell-edge user performance. More specifically, the concept is explored further in this paper analyzing the impact of different cell-sweeping configurations and evaluating the potential benefits towards achieving energy efficiency. By means of system level computer simulations, it is shown that cell-sweeping provides energy savings of 11% and 26.5% for a similar average and cell-edge user throughput performance, respectively, when compared to the conventional static cell deployment in a typical urban macro cell scenario.

Detecting and diagnosing the root cause of failures in mobile networks is an increasingly demanding and time-consuming task, given its technological growing complexity. This paper focuses on predicting and diagnosing low User Downlink (DL) Average Throughput situations, using supervised learning and the Tree Shapley Additive Explanations (SHAP) method. To fulfill this objective, Boosting classification models are used to predict a failure/non-failure binary label. The influence of each counter on the overall model’s predictive performance is performed based on the TreeSHAP method. From the implementation of this technique, it is possible to identify the main causes of low throughput, based on the analysis of the most critical counters in fault detection. Furthermore, from the identification of these counters, it is possible to define a system for diagnosing the most probable throughput degradation cause. The described methodology allowed not only to identify and quantify low throughput situations in a live network due to the occurrence of misadjusted configuration parameters, radio problems and network capacity problems, but also to outline a process for solving them.

Two oscillator circuits designed in 45 nm technology incorporating an integrated capacitive vibrating Micro Electro Mechanical (MEMS) resonator for microprocessor applications are presented. The general topology of the oscillator is based on a shunt-shunt feedback transimpedance amplifier with an automatic gain control circuit to ensure linear operation of the integrated resonator to reduce the oscillator 1/f3phase noise component introduced by the resonator nonlinear capacitive transducer. Two different topologies for the transimpedance amplifier are presented: the first topology uses a self biased fully differential amplifier while the second topology uses a multi stage gm-boosting amplifier with a negative feedback amplifier for self biasing. The designed circuits operate robustly across all process corners and across 120°C temperature range from -10°C to 110°C while consuming less than 8 mW power and occupying an area of 300um×255um and phase noise of -120dBC/Hz at 200KHz offset. The designed circuits are the first implementation of a MEMS based oscillator in deep submicron processes showing robust performance across all process corners and variations.

The mobile computing device market has been growing rapidly. This brings the technologies that optimize system energy to the forefront. As circuits continue to scale in the future, it would be important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels. Schedule slacks in codes executing in VLIW architectures present an opportunity for such an integration. In this paper, we present three compiler-directed techniques that take advantage of schedule slacks to optimize leakage and dynamic energy consumption. Integer ALU (IALU) components operating with multiple supply voltages are designed to provide different low-energy versions that possess different operational latencies. The goal of the first technique explored is to maximize the number of operations mapped to IALU components with the lowest energy consumption without extending the schedule length. We also consider a variant of this technique that saves more energy at the cost of some performance loss. The second technique uses two leakage-control mechanisms to reduce leakage energy consumption when no operations are scheduled in the component. Our evaluation of these two approaches, using fifteen benchmarks, shows that based on the number and duration of slacks, the availability of low-energy functional units and the relative magnitude of leakage and dynamic energy, either leakage or dynamic energy consumption, will provide more energy gains. Finally, we provide a unified energy-optimization strategy that integrates both dynamic and leakage energy-reduction schemes. The proposed techniques have been incorporated into a cycle accurate simulator using parameters extracted from circuit-level simulation. Our results show that the unified scheme generates better results than using either of dynamic and leakage energy-reduction techniques independently.

The impact of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) is evaluated by determining limits and benefits, in terms of the potential leakage reduction, performance penalty, and area and power overhead in 0.25um, 0.18um, and 0.07um technologies. HSPICE simulation results and estimations with various functional units and memory structures are presented to support a comprehensive analysis.

In embedded and portable applications, energy dissipation is a major design constraint. Designers must consider energy consumption. SimplePower evaluates the energy considering the system as a whole rather than just as a sum of parts, and concurrently supports both compiler and architectural experimentation. It includes a transition-sensitive, cycle-accurate datapath energy model that interfaces with analytical and transition-sensitive energy models for the memory, clock and bus subsystems, respectively. We analyzed the energy consumption of 10 codes from the multidimensional array domain, and find datapath energy hotspots, bottlenecks and helpful features. Optimized codes saved 21 percent more energy using the most recently used way-prediction cache scheme as compared to executing unoptimized codes from the multidimensional array domain.

Summary form only given. A PLL power model that accurately estimates the power consumption during both lock and acquisition states is presented. The model is within 5% of circuit level simulation (SPICE) values. No significant power overhead (+/-5% of the power consumed at the final frequency) is incurred during the acquisition process.

Power is considered to be the major limiter to the design of faster and more complex processors in the near future. In order to address this challenge, a combination of process, circuit design and micro-architectural changes are required Consequently, to focus optimization efforts in the right direction, the models proposed and studies performed in this work are a first step for understanding the relative importance of leakage and dynamic energy in future technologies. Further, we analyze the effectiveness of two energy reduction mechanisms that employ voltage scaling, namely, supply and threshold voltage selection. We consider the impact of imminent technology changes and packaging improvements while showing that neglecting the impact of temperature may lead to underestimating power savings by up to 19.5%.

The mobile computing device market is projected to grow to 16.8 million units in 2004, representing an average annual growth rate of 28% over the five year forecast period. This brings the technologies that optimize system energy to the forefront. As circuits continue to scale in future, it would be important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels. Schedule stacks in codes executing in VLIW architectures present an opportunity for such an integration. In this paper, we present compiler-directed techniques that take advantage of schedule slacks to optimize leakage and dynamic energy consumption. The proposed techniques have been incorporated into a cycle accurate simulator using parameters extracted from circuit level simulation. Our results show that a unified scheme that uses both dynamic and leakage energy reduction techniques is effective in reducing energy consumption.