In this paper, a real-time multi-individual boxing classification system, which is based on FPGA, using electromyography (EMG) signals and Inertial measurement units (IMUs) is presented. The proposed system is realized on the Xilinx Ultra96 single computer board, combining EMG signals and acceleration to classify different boxing actions. An improved attitude update algorithm based on extended Kalman filter (EKF) is used to calculate the change in roll angle of the IMU during a certain punch and a correlation-based method is then applied to classify between different types of punches. The presented system achieves a latency of about 21.7ms with an accuracy of 80.0% on a laptop with AMD R7-7735H, 16GM RAM and about 74.5ms with an accuracy of 68.3% on FPGA respectively in a multi-person boxing real-time monitoring scenario. The algorithm enables real-time boxing classification with high accuracy using only wearable sensors, which enhances the portability of the whole system and can be used in real-time scenarios.

Eye tracking technique is showing broad application potential in daily life. This work proposes an FPGA-based eye gaze tracking system with a differential convolutional neural network structure, which is naturally compatible with calibration operation. Each newly acquired eye image is fed into the proposed algorithm together with the pre-calibrated eye sample as a reference to obtain the relative gaze direction. The final processing output is generated by combining the results of several reference samples. Our design reports an angular gaze tracking accuracy of 3.28° and 3.05° on MPIIGaze and a self-built dataset, respectively. The entire system is integrated on a Xilinx Ultra 96 single computer board with FPGA for acceleration. The total weight of the board is 123.3 grams. The system achieves a processing speed of 15.2 frames per second.

This paper proposes an interface IC that implements a Current Convey and Resistor (CC+R) based potentiostat architecture for the detection of a maximum 2mA DC current with an Irmsof 50nA. The relative reference bias design based on the OECT source reduces the relative voltage instability caused by switching between channels. The programmable output stage based on the adjustable gain amplifier (PGA) and 13-bit Successive Approximation Register Analog-to-digital converter (SAR ADC) achieves a dynamic range of more than 80dB. The detection of the Tumor Necrosis Factor-alpha (TNF-α) based on this interface IC achieves the highest 10fMol sensitivity.

Multichannel neural signal acquisition and processing play a pivotal role in advancing neuroscience research. This article proposes a 112-channel system-on-chip (SoC) design for neural signal acquisition and processing, comprising full-channel read-out circuits, neural signal-processing accelerators, and a 32-bit RISC-V core. A clock-domain-crossing (CDC) structure is devised to minimize data storage overhead in read-out circuits, facilitating comprehensive data acquisition and high-throughput simultaneous transmission from all channels. The channel-specific processing unit incorporates hardware-efficient designs for lossless compression, spike detection, and extraction of spike features. A multistage predictor module serves the dual purpose of narrowing data distribution during compression and signal augmentation during spike detection. The proposed design was fabricated in 40-nm technology with an area of 6.67 mm2. The acquisition of 112 channels achieves a peak data rate of 57.3 Mbps, with a total power consumption of 3.07 mW, wherein 0.87 mW is attributed to the read-out circuits. The processing accelerators feature an area consumption of 0.011 mm2/ch, and a minimal power consumption of only$0.2~{\mu }$W/ch under a 32-kHz clock. The effectiveness of the proposed design is validated through in vivo recording experiments conducted on rats by integrating with flexible implantable electrodes.

This paper proposed a wireless 16-channel im-plantable system for long-term neural recording. In order to achieve stable and reliable neural signal acquisition, the im-plantable microsystem consists of an analog front end (AFE), a transmitter (TX), a small battery and a coil for energy harvesting to charge the battery. The AFE integrates 16-channel low-noise amplifiers (LNA), a SAR ADC and a digital interface. The TX integrates a rectifier, a bandgap voltage reference, regulators and a 427 MHz OOK modulated transmitter. The AFE and TX chips were fabricated in 180-nm technology. All the required functional modules are integrated in the chips with off-chip crystal, coil and antenna. The proposed microsystem weighs 2.1 g without a battery, and 3.7 g including the battery. The dimension is$20\times 18\times 7$mm 3. The total current of the system is 1.13 mA, and the battery life is about 50 hours with a capacity of 60 mA$h$. The charging current is 10mA under wireless power transmission.

This paper proposed a multiple-mode animal behavior analysis system integrating a wireless bio-potential recorder and two 120fps video streams. A 16-channel analog-front-end (AFE) featuring a chopper low noise amplifier (LNA) and a 12-bit successive approximation analog-to-digital converter (SAR ADC) is designed as the sensor interface. Bluetooth Low Energy (BLE) based in-the-air protocol is implemented for wireless data transmission. A precise synchronization method is proposed featuring a millisecond level synchronization accuracy between the video frames and the acquired bio-potential. The compact wireless bio-potential recorder features a size of 2 × 2.5 × 1cm and a battery life of 9 hours. In-vivo test has been performed on rats with long-term implantable electrodes. The proposed system successfully recorded the electroneurogram (ENG) signal from sciatic nerves and electromyography (EMG) signal from leg muscles. Also video-based gait analysis was performed and provided the labels to train an EMG-based gait phase classifier.

This paper proposed a miniature neural interface system. A single chip neural recording SoC was fabricated in 40nm CMOS process with an area of 3mm×3mm. It integrated a 16-channel analog front end (AFE), and a low power constant envelope polar transmitter. The general form of continuous phase modulation was used as the modulation scheme. Algorithms for receiver including frequency offset calibration, frame synchronization, and symbol demodulation were proposed and implemented on a software-defined radio platform. Simulation results showed that a bit error rate of $10^{-4}$ is achieved at the signal to noise ratio of 19 dB at high data rate mode of 971.4 kbps. A graphic user interface was designed for channel decoding and real-time display. Experimental results showed that the input referred noise of the AFE is 2.87$\mu V_{rms}$, and the energy efficiency of the transmitter is 2. 8nJ/bit. The proposed chip consumes 5. 47mW power in total in its maximum workload. The neural signal can be correctly decoded at least at a RSSI (Received Signal Strength Indicator) of -95dBm, and a working distance of 8 m. In-vivo tests on rat have been conducted, showing a good usability of the proposed system.

High-voltage power lines are essential for people’s daily life. Unmanned aerial vehicle (UAV) airborne light detection and ranging (LiDAR) is widely used in power line management. The workload of LiDAR point cloud data processing is very large, however, most of the data needs to be sent back to the local or cloud for processing, which produce great latency. In this work, an FPGA-based LiDAR point cloud data processing system for power line extraction is proposed. The original points are classified into foreground points including power lines and power towers, and background points including ground, vegetation and other points. The raw point data is grid grouped locally. Feature extraction algorithm is applied to each grid in parallel. The precision, recall and F1-score are 99.46%, 87.55%. 93.13%, respectively. The proposed system achieves a processing speed of 37.49K points per second. The entire system is integrated on a Xilinx Ultra 96 single computer board with FPGA for acceleration. The total weight of the board is 123.3 grams.

This paper proposes SaleNet - an end-to-end convolutional neural network (CNN) for sustained attention level evaluation using prefrontal electroencephalogram (EEG). A bias-driven pruning method is proposed together with group convolution, global average pooling (GAP), near-zero pruning, weight clustering and quantization for the model compression, achieving a total compression ratio of 183. 11x. The compressed SaleNet obtains a state-of-the-art subject-independent sustained attention level classification accuracy of 84.2% on the recorded 6-subject EEG database in this work. The SaleNet is implemented on a Artix-7 FPGA with a competitive power consumption of 0.11 W and an energy-efficiency of 8.19 GOps/w.

This paper proposed a fully integrated MBAN (2360–2400 MHz) continuous phase modulated transmitter (TX) with tunable less than 0dBm output power for medical band. A duty-cycle tuning strategy was proposed for the power amplifier (PA) featuring adaptive optimized efficiency for different output powers. A fully on-chip transformer-based match network was proposed to suppress the 2nd harmonic using a series$LC$resonator and to suppress the 3rd harmonic by introducing a transformer inter-winding capacitor feedback path. A fractional-N all-digital phase locked loop (ADPLL) with a transformer-based digitally controlled oscillator (DCO) is employed to reduce power consumption as well as improve modulation quality. The transmitter was fabricated in 40-nm CMOS technology, occupying an active area of 0.48mm2. Experimental results show a 26% drain efficiency with −10dBm PA output and 4dB tunable range. A 2mW total power consumption was measured with a TX efficiency of 5% and an energy efficiency of 2nJ/bit. The measured 2nd and 3rd harmonic distortion of the output were −44.3dBm and −57.2dBm, respectively, with on-chip matching network. The measured FSK error of CPM was 2.3% with an M of 2 and 1.57% with an M of 4.

In this work, a real-time movement decomposition-based automatic behavior analysis system is proposed. The proposed method is evaluated on a Morris water maze experiment with rat. The system integrated a high-speed tracker, a feature extraction module, and a classifier on a Xilinx Ultra-96 single computer board with a field-programmable gate array (FPGA). The high-speed tracker includes a movement predictor based on motion features and pose features, and a fast-checking algorithm to evaluate whether the tracking result is correct or not. A faster region-based convolutional neural network (Faster-RCNN)-based detector is used for initializing the tracker. The feature extraction module integrated a CNN-based feature point recognition network and a motion feature computing module. Motion and pose feature are calculated with the result of the feature points. The proposed system achieves a 66.2-frames/s processing speed, and the average point detection error is 4.01 pixels. For each video, the classification and regression tree (CART)-based classifier gives an explorative stage in five categories, which represents the rat’s strategy of exploration in Morris water maze task. This work focuses on a real-time local computing system design on small-scale datasets.

Image based motion tracking of human skeletons is widely used in biomechanical research, while electromyography (EMG) contains direct reflections of the muscle activities. A combination of image and EMG data enables a more effective way to quantitatively evaluate the recover level of patients with movement disorders, such as post-stroke patients. This paper proposed a wireless multiple-mode human behavior evaluation system enables simultaneously acquisition of multiple image sensor data and acquisition of EMG data from different muscles. Several wireless wearable EMG sensor nodes are attached to different muscles-of-interest over the body. Each EMG sensor node features an individual acquisition channel. The collected data are transferred through Bluetooth Low Energy. Each EMG node features a size of 2cm × 3cm × 1cm with a weight of 16 gram and a battery life of 20 hours. Two Wi-Fi based wireless image sensors are used. A convolutional neural network based human pose estimation method is proposed to track the skeleton motion features from the captured streams. The fully wireless nature guarantees the usability and flexibility of the proposed system. A data collection and remote analysis platform is also developed for remote support. The proposed system has been tested on patients recovering from stroke.

This paper proposed an epilepsy seizure detection ASIC design using only one channel EEG signal as input. The proposed design consists of 10 sub-bands FIR filters and band energy feature extraction engines. A MAC is utilized as a linear SVM classifier. The design was fabricated in TSMC 180nm technology with a power consumption of 3.09 μJ/Classification. According to experimental results, the average sensitivity is reduced by less than 10% while the area is reduced by 70%. With patient-specific configurable parameters, a higher than 90% dection sensitivity was achieved on half of the patients in the testing dataset.

The difference in EEG data among subjects and sessions is an essential factor affecting the accuracy in neural signal analysis. This paper proposed a Tri-FeatureNet, an adversarial learning-based feature extraction algorithm to learn representations invariant to subjects and sessions for sleep staging. The proposed work improves the algorithm's robustness to individual differences. The invariant features are combined with the subject-specified features and the temporal features to further compensate for the loss of sleep information during adversarial training. The proposed model makes use of the temporal information in EEG signals and sleep staging sequences at the same time. This is the first time that adversarial training was proposed to extract the task-related features for different subjects and different sessions in sleep staging. The proposed algorithm was implemented in a portable sleep staging system. Experimental results illustrated an 82.9% ACC in sleep staging task with a single-channel EEG signal.

A competition-cooperation teacher-student model is proposed for knowledge transfer between channels for sleep staging. The teacher model was trained simultaneously with competitor and cooperator student models. One extra “competitor” student model was added to the traditional teacher-student model. The performance of the teacher model can be optimized during the competition with the competitor model. The over-fitting of the student model is greatly reduced in cooperation with the teacher model. A three-step competition-cooperation training process was proposed to optimize the performance of both the teacher model and the student models. The experimental results demonstrate a 2.7% and a 1.6% improvement of the accuracy for the teacher model and the student model, respectively. A state-of-the-art sleep staging accuracy of 83.7% with single-channel input and 85.9% with multi-channel inputs was achieved by the proposed algorithm.

This paper presents a power efficient 12-bit successive aproximation register analog-to-digital converter (SAR ADC) operated at a supply voltage of 0.6V. A binary-scaled redundant technology for SAR ADC is proposed based on split-capacitor DAC architecture. It suppresses the decision error without sacrificing the resolution. In addition, a feedback controlled bias technique is applied to the comparator reducing the power consumption for comparison by 21.6%. The proposed ADC was fabricated in 0.18μm CMOS technology, occupying an core area of 0.07mm2. The measured DNL and INL is +0.46/-0.50 LSB and +0.98/-0.95 LSB, respectively. A SINAD of 68.1dB and SFDR of 83.0dB are achieved, respectively, while operating at a sampling rate of 100kS/s. The power consuming of the proposed ADC is 1.35uW, resulting in an FOM of 6.5fJ/Conversion-step.

This paper presents the design of a low-noise chopper amplifier for neural signal acquisition in the presence of the in-band stimulation artifacts that exist in the closed-loop neuromodulation system. In order to avoid saturation due to the artifacts, the gain of the amplifier is designed to be 26dB. A modified positive feedback loop is introduced to boost both inband and DC input impedance. The Gm-C integrator without external capacitors is used in the DC-Servo-Loop (DSL) to filter out the electrode offset. To further enhance the linearity, the voltage divider technique is employed at the input of the Gm-C integrator. The proposed work was fabricated using a 0.18um CMOS process. The amplifier consumes 3.42μW under 1.8V supply voltage, while occupying an area of 0.219mm2. The measured input-referred noise is 1.12μVrms(1 Hz-200 Hz) and 4.65μVrms(200 Hz-5 kHz). A DC input impedance of 90MΩ, a CMRR of 103dB, and a PSRR of 78dB are achieved as well.

This paper presents a novel neuroprosthetic system for perception encoding. The system consists of a wireless waterproof bi-directional neural interface and an object tracking image sensor. The neural interface features a fully programmable 8-channel neural stimulator, a compliance voltage and impedance monitoring module, a 16-channel neural recording front-end, and a duplex wireless transceiver. The image sensor features a 180×180 pixel array, with in-pixel comparator for energy efficient color thresholding based object detection tracking. A unique experiment was designed in which rats navigate a water maze using only brain stimulation to inform their location relative to a hidden platform. Custom hardware and software have been developed to support the investigation, with special attention paid to the safety of the animals during the experiment. The proposed chip designs have been fabricated in 180nm CMOS technology. This work demonstrates a novel experimental paradigm, and that the developed wireless neuroprosthetic system can be used to conduct extensive sensory encoding experiments in freely behaving animals.

This paper presents a fully integrated wireless sensor brain machine interface system to restore continuous somatosensory feedback from the hand. A wireless bi-directional neural interface system-on-chip (SoC) and a wireless sensor node design are described in this work. The neural interface integrates a 16-channel neural recording front-end, a 16-channel electrical stimulation back-end, a successive approximation analog-to-digital converter (ADC), a custom digital controller, and an ultra-wide band (UWB) wireless transceiver. The sensor node features a custom designed optical force sensor, a low-power level-crossing ADC, an UWB transmitter, and analog interface to off-chip accelerometers. The optical force sensor is developed in standard CMOS with low-cost post fabrication. Multiple sensor nodes can be used to trigger pre-defined microstimulation in different brain areas for restoring finger sensation. The prototypes have been fabricated in 180nm standard CMOS technology. Bench testing and In-Vivo experimental results are presented in this paper. The system was designed to investigate the first chronic interface to the cuneate nucleus of macaques, and showed a promising solution for sensation restoration in future neuroprosthetics.

This paper presents a 12-channel, low-power, high efficiency neural signal acquisition front-end for local field potential and action potential signals recording. The proposed neural front-end integrates low noise instrumentation amplifiers, low-power filter stages with configurable gain and cut-off frequencies, a successive approximation register (SAR) ADC, and a realtime compressed sensing processing unit. A capacitor coupled instrumentation amplifier integrated input impedance boosting has been designed, dissipating 1μA quiescent current. An input referred noise of 1.63μV was measured in the frequency band of 1Hz to 7kHz. The noise efficiency factor (NEF) of the amplifier is 0.76. The SAR ADC achieves an ENOB of 10.6-bit at a sampling rate of 1MS/s. A compressed sensing processing unit with configurable compression ratio, up to 8x, was integrated in the design. The design has been fabricated in 180nm CMOS, occupying 4.5mm×1.5mm silicon area. A portable neural recorder has been built with the custom IC and a commercial low-power wireless module. A 4.6g lithium battery supports the device for a continuous compressed sensing recording up to 70 hours.

In this paper, a wireless electrogoniometer is described using a pair of ultra-wide band (UWB) wireless smart sensor nodes that are interfaced to low power 3-axis accelerometers. A high resolution SAR ADC as well as a low power asynchronous continuous sampling event-driven ADC are integrated for the digitization of the input signal under different operation modes. An anti-self-locking circuit is included in the asynchronous event-driven ADC to improve the robustness. A tri-channel UWB transceiver is designed particularly for the data transmission of the 3-axis accelerometers. A power consumption of 4.6pJ/bit is achieved for the transmitter at 10Mbps while operating under 1.2V power supply. The receiver power consumption can be as low as 0.32nJ/bit at 10Mbps under 1.8V supply. To demonstrate one application of the device, the electrogoniometer was used to quantify the in-vivo response of a somatosensory neuron to joint angle changes.

CMOS Polarization image sensors can detect the polarization of an incident light, from which a lot of information can be derived about the properties and shape of the images objects. This paper proposes a current mode polarization analyzer, based on a three-parameter polarization analysis methodology. The procedure of the calculation of the intensity, polarization degree, and the polarization angle is optimized in a format for hardware friendly implementation. The proposed analysis procedure is implemented using only absolute adder/subtractors and multiplier/dividers. In this work, the multiplier/divider is performed in two modes: i) geometric mean calculation mode, and ii) square/divider mode. Both a parallel implementation, which employs five multiplier/divider, for the optimization of processing efficiency, and a serial implementation, which employs two multiplier/divider, for the optimization of power efficiency, are designed and compared. A prototype chip of the proposed design was implemented in 0.5μm 3M2P standard CMOS technology, occupying a silicon area of 150 × 140 μm2.

In this paper, a general purpose wireless Brain-Machine-Brain Interface (BMBI) system is proposed. The system provides all the necessary hardware for a closed-loop sensorimotor neural interface. The system integrates a neural signal analyzer, two neural stimulators with different specifications, multiple body area sensory devices and a user-friendly computer interface. The neural signal analyzer features four channel analog frontend with configurable bandpass filter, gain stage, digitization resolution, and sampling rate. Digital filtering, neural feature extraction, spike detection, sensing-stimulating modulation, and compressed sensing measurement are realized in a central processing unit integrated in the analyzer. Flash memory card is activated for low power operation, compressed sensing recovery verification and/or data backup. An 8-channel stimulator with high driving capability (±10 mA with compliance voltage ±22V), and a 2-channel stimulator for deep brain stimulation are included in the proposed system. Both stimulators are capable of delivering bipolar, biphasic capacitive coupled current pulses in programmable pulse shape, amplitude, width, pulse train frequency and latency. Multi-functional wireless sensor node, including an accelerometer, a temperature sensor, and a general sensor extension port has been designed. Surveillance camera is implemented for the monitoring of the animal's behavior. A userfriendly computer interface is designed to monitor, control and configure all aforementioned devices via wireless link. Wireless closed-loop operation between the sensory devices, neural stimulators, and neural signal analyzer can be configured. Bench test and in vivo experiments are performed to verify the functions and performance of the system.

In this paper, a bioinspired monolithic complementary metal-oxide-semiconductor (CMOS) polarization image sensor is described as a solution to real-time polarization image capture. Metallic wire-grid gratings are integrated onto standard CMOS image sensor arrays with different orientations. A numerical analysis is performed to guide the design of the wire-grid arrays. Experimental results from different CMOS processing units are compared. A current-mode polarization processing unit is designed, fabricated, and tested in order to perform the extraction of the polarization characteristics from the captured intensities. This paper illustrates how polarization image processing can be used to monitor live cells. Several polarization processing methods with different computational complexity and data requirements have been applied and compared.

In this paper, we propose a novel low power multimode CMOS smart image sensor node with integrated focal-plane motion detection and video compression. An 80×80 image pixel array is fabricated in 0.5 μm 3M2P standard CMOS technology, occupying 3×3 mm2silicon area. The proposed imager enables various operational modes, including 1) event generator mode, 2) motion tracking mode and 3) video output mode in full-resolution or compression by region of interest (ROI). An ultra low power focal-plane motion detection block, consisting of analog memory and dual-threshold comparator, is integrated in the pixel-level circuit for on-chip motion detection. A hardware-friendly motion tracking algorithm is developed that indicates ROIs according to a strategy based on the detection results. A 12-bit on-chip, off-array ADC is employed to convert the captured light intensity into digital readouts. In order to further reduce the power consumption, lower image resolution is used under the first two modes. A trade-off analysis between the image resolution and detection accuracy is proposed in this paper. In simulation, the total power consumption is 10μW at a frame rate of 30fps and a supply voltage of 3.3V in motion tracking mode. A compression ratio of 14% and an average PSNR of 42dB is achieved in compressive video output mode.

A voltage controlled MEMS oscillator (VCMO) fabricated in 65nm CMOS process is proposed in this paper. The piezoelectric aluminum nitride (AlN) Contour-Mode MEMS resonator based oscillator can be operated under multiple frequencies from 204MHz, to 517MHz, to 850MHz. A maximum overall tuning range of 611ppm is achieved at a center frequency of 204MHz. The proposed oscillator operates in the sub-threshold region, resulting in a power consumption of 47μW measured under a 0.55V power supply, which is the lowest reported in literature for an application in the 200MHz range. The measured oscillator phase noise is -77dBc/Hz at 1kHz offset from the 204MHz carrier.

The concept of compressive acquisition image sensor is to compress data while sensing and prior to storage. In this paper, the concept of compressive acquisition image sensor is developed, implemented and experimentally validated for both spatial and temporal domains. In the proposed scheme, the image sensor array is divided into quadrants integrating logic circuitry which performs online spatial compression of the raw data prior to storage. The quadrants are subsequently further classified into background/non-background quadrants by an off-array judge logic which enables to adaptively track the associated temporal information. Temporal redundancy between frames is hence removed in the readout phase. The proposed compressive acquisition algorithm is simulated and experimentally validated for both spatial and temporal domains through a hardware prototype. Experimental results show that the proposed algorithm enables more than 50% memory saving at a PSNR level of 26 dB with around 0.5 BPP. This result not only greatly reduces the memory requirements for a digital pixel CMOS image sensor, but also results in area saving as data is only stored after being compressed.

In this paper, a new design paradigm referred to as compressive acquisition CMOS image sensors is introduced. The idea consists of compressing the data within each pixel prior to storage, and hence, reducing the size of the memory required for digital pixel sensor. The proposed compression algorithm uses a block-based differential coding scheme in which differential values are captured and quantized online. A time-domain encoding scheme is used in our CMOS image sensor in which the brightest pixel within each block fires first and is selected as the reference pixel. The differential values between subsequent pixels and the reference within each block are calculated and quantized, using a reduced number of bits as their dynamic range is compressed. The proposed scheme enables reduced error accumulation as full precision is used at the start of each block, while also enabling reduced memory requirement, and hence, enabling significant silicon area saving. A mathematical model is derived to analyze the performance of the algorithm. Experimental results on a field-programmable gate-array (FPGA) platform illustrate that the proposed algorithm enables more than 50% memory saving at a peak signal-to-noise ratio level of 30 dB with 1.5 bit per pixel.

In this paper, the architecture of a digital pixel sensor (DPS) array with an online 1-bit predictive coding algorithm using Hilbert scanning scheme is proposed. The architecture of the sensor array reduces by more than half the silicon area of the DPS by sampling and storing the differential values between the pixel and its prediction, featuring compressed dynamic range and hence requiring limited precision (only 1-bit signed value in the proposed architecture as compared to 8-bit unsigned full precision). Hilbert scanning is used to read-out the pixel's value, hence avoiding discontinuity in the read-out path, which is shown to improve the quality of the reconstructed image. The Hilbert scanning path is all carried out by hardware wire connection without increasing the circuit complexity of the sensor array. Reset pixels are inserted into scanning path to overcome the error accumulation problem inherent in predictive coding. System level simulation results show a PSNR of around 25dB can be reached while using the proposed 1-bit Hilbert predictive coding algorithm. VLSI implementation results illustrate a pixel level implementation featuring a pixel size reduction of 67% with a fill-factor of 40% compared with a standard PWM DPS architecture.