Storage I/O performance remains a key factor that determines the overall user experience of a computer system. This is especially true for mobile systems as users commonly browse and navigate through many high-quality pictures and video clips stored in their device. The appetite for more appealing user interface has continuously pushed the mobile storage interface speed up; emerging UFS 2.0 standard provisions a maximum bandwidth of as high as 1,200 MB/s. In this work, we propose, design, and implement a mobile storage architecture that leverages the high-speed DRAM interface for communication, thus substantially expanding the storage performance headroom. In order to effectively turn the existing DRAM interface into a storage interface, we design a new storage protocol that runs on top of the DRAM interface. Our protocol builds on a small host interface buffer structure mapped to the system's memory space. Based on this protocol, we develop and fabricate a storage controller chip that natively supports the LPDDR3 interface. We also develop a host software stack (Linux device driver and boot loader) and a host platform board. Finally we show the feasibility of our proposal by constructing a full Android system running on the developed storage device and platform. Our detailed evaluation shows that the proposed storage architecture has very low protocol handling overheads and compares favorably to a UFS 2.0 device. The proposed architecture obviates the need for implementing a separate host-side storage controller on a mobile CPU chip.

Abstract 3D objects of the same kind often have different topologies, and finding correspondence between them is important for operations such as morphing, attribute transfer, and shape matching. This paper presents a novel method to find the surface correspondence between topologically different surfaces. The method is characterized by deforming the source polygonal mesh to match the target mesh by using the intermediate implicit surfaces, and by performing a topological surgery at the appropriate locations on the mesh. In particular, we propose a mathematically well‐defined way to detect the topology change of surface by finding the non‐degenerate saddle points of the velocity fields that tracks implicit surfaces. We show the effectiveness and possible applications of the proposed method through several experiments.

Quality power estimation is a basis of efficient power management of electronic systems. Indirect power measurement, such as power estimation using a CPU performance monitoring unit (PMU), is widely used for its low cost and area overheads. However, the existing CPU PMUs only monitor the core and cache activities, which result in a significant accuracy limitation in the system-wide power estimation including off-chip memory devices. In this paper, we propose an on-chip bus (OCB) PMU that directly captures on-chip and off-chip component activities by snooping the OCB. The OCB PMU stores the activity information in separate counters, and online software converts counter values into actual power values with simple first-order linear power models. We also introduce an optimization algorithm that minimizes the energy model to reduce the number of counters in the OCB PMU. We compare the accuracy of the power estimation using the proposed OCB PMU with real hardware measurement and cycle-accurate system-level power estimation, and demonstrate high estimation accuracy compared with CPU PMU-based estimation method.

We analyze the effect of input voltage and interruption processes that frequently occur while driving, and how they decrease the lifetimes of halogen lamps used in automotive headlights. First, we established estimated lifetimes of halogen lamps regarding short-term use, taking accelerator use into consideration. Through failure analysis, we discovered that the main cause of failure in open halogen lamps were the single wire filaments. We estimated lifetimes, factoring in acceleration in both continuous running and on and off conditions to examine life shortening due to the interruptions. The result of comparing lifetimes of continuously running lamps and on-off lamps found that lamps that were turned off and on had roughly a 31% decrease in life span. This shows that the inrush current generated when turning on a lamp is the main stress shortens the lifetime of lamp. Therefore, automobile manufacturers should provide information about lamp replacement cycles to customers or they should determine lifetimes by conducting additional on-off tests rather than simple continuous tests to find products with longer replacement cycles.

In this paper we propose an on-chip bus PMU which makes accurate estimates of system power consumption from a first-order linear power model by utilizing system-level activity information exchanged on the on-chip bus. It can easily be customized for different on-chip and off-chip memory devices, and is not dependent on a specific CPU core. We model memory devices using energy state machines, describe them in XML, and use that description automatic synthesis of the PMU.We compare the short-term accuracy of the proposed PMU with a cycle-accurate system-level power estimator, and assess its long-term accuracy with a real hardware prototype. Experimental results show that the the power estimation deviates less than 5% from real measurements.

Energy-aware task scheduling significantly reduces the total energy required by a system to perform a particular job, by dynamically changing the clock frequency and supply voltage at which the CPU operates. But this causes significant fluctuation of the current drawn from the power source, so that no single voltage regulator can achieve satisfactory efficiency over the entire range of operating currents.

The lifetime of a stand-alone media recorder is a function of both the battery size and flash memory size. In this paper, we present a power management framework for media recorders that significantly enhances their lifetime while minimizing the flash memory usage and maintaining the same level of recording quality. This is achieved by implementing a mixture of encoding algorithms of different complexities that generate data with different compression ratios, and in turn balancing the energy consumption and the flash memory usage.

Memory devices often consume more energy than microprocessors in current portable embedded systems, but their energy consumption changes significantly with the type of transaction, data values, and access timing, as well as depending on the total number of transactions. These variabilities mean that an innovative tool and framework are required to characterize modern memory devices running in embedded system architectures. We introduce an energy measurement and characterization platform for memory devices, and demonstrate an application to multilevel-cell (MLC) flash memories, in which we discover significant value-dependent programming energy variations. We introduce an energy-aware data compression method that minimizes the flash programming energy, rather than the size of the compressed data, which is formulated as an entropy coding with unequal bit-pattern costs. Deploying a probabilistic approach, we derive energy-optimal bit-pattern probabilities and expected values of the bit-pattern costs which are applicable to the large amounts of compressed data typically found in multimedia applications. Then we develop an energy-optimal prefix coding that uses integer linear programming, and construct a prefix-code table. From a consideration of Pareto-optimal energy consumption, we can make tradeoffs between data size and programming energy, such as a 41% energy savings for a 52% area overhead.

We discover significant value-dependent programming energy variations in multi-level cell (MLC) flash memories, and introduce an energy-aware data compression method that minimizes the flash programming energy rather than the size of the compressed data. We express energy-aware data compression as an entropy coding with unequal bit-pattern costs. Deploying a probabilistic approach, we derive the energy-optimal bit-pattern probabilities and the expected values of the bit-pattern costs for the large amounts of compressed data which are typical in multimedia applications. Then we develop an energy-optimal prefix coding that uses integer linear programming, and construct a prefix code table. From a consideration of Pareto-optimal energy consumption, we make tradeoffs between data size and programming energy, such as a 35% energy saving for a 50% area overhead.

Recent wireless sensor nodes, equipped with ultra-low-power (ULP) RISC microcontrollers, do not generally support DVS (dynamic voltage scaling), though the ULP microcontrollers have ideal energy-voltage-frequency characteristics for DVS. In general, an output-adjustable DC-DC converter is hardly all affordable in such sensor nodes, and surprisingly light current consumption makes the DC-DC converter operate in a very inefficient region.

Most existing dynamic voltage scaling (DVS) schemes for multiple tasks assume an energy cost function (energy consumption versus execution time) that is independent of the task characteristics. In practice the actual energy cost functions vary significantly from task to task. Different tasks running on the same hardware platform can exhibit different memory and peripheral access patterns, cache miss rates, etc. These effects results in a distinct energy cost function for each task.We present a new formulation and solution to the problem of minimizing the total (dynamic and static) system energy while executing a set of tasks under DVS. First, we demonstrate and quantify the dependence of the energy cost function on task characteristics by direct measurements on a real hardware platform (the TI OMAP processor) using real application programs. Next, we present simple analytical solutions to the problem of determining energy-optimal voltage scale factors for each task, while allowing each task to be preempted and to have its own energy cost function. Based on these solutions, we present simple and efficient algorithms for implementing DVS with multiple tasks. We consider two cases: (1) all tasks have a single deadline, and (2) each task has its own deadline. Experiments on a real hardware platform using real applications demonstrate a 10% additional saving in total system energy compared to previous leakage-aware DVS schemes.

Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops. This results in unwanted glitch propagation along the LUTs, and wastes power. This paper proposes a flip-flop insertion, we propose insertion of new flip-flops between adjacent existing flip-flops to minimize glitch propagation and power loss. Each new flip-flop is timed by a phase-shifted clock with the phase calculated from the delays of LUTs and routing paths. This is different from traditional retiming methods that use the original clock or an 180-degree clock for the new flip-flops, and thus alters the original pipeline structure and synchronization. We start from a post-layout design, retiming its clock frequency and timing behavior. Multiple flip-flop insertion is an NP-complete problem because each new flip-flop affects the delays in the design. We have devised a glitch generation and propagation model for LUT-based FPGAs that take account of path delays while supporting reasonable complexity. We propose effective heuristics for flip-flop insertion and clock phase selection. Full-chip measurements, including all the overheads associated with the inserted flip-flops, show that our approach shows up to 38% of the total dynamic power. We have analyzed our scheme, showing the mechanics of clock assignment and glitch minimization, and the sources of power reduction.

Dynamic supply voltage scaling (DVS) is one of the best ways to reduce the energy consumption of a device when there is a super-linear relationship between energy and supply voltage, and a pseudo-linear relationship between delay and supply voltage. However, most DVS schemes scale the clock frequency of the supply-voltage-clock-scalable (SVCS) CPU only and do not address the energy consumption of the memory. The memory is generally non-supply-voltage-scalable (NSVS), but its energy consumption is variable to its clock frequency and the total execution time. Thus, DVS for an SVCS CPU cannot achieve an optimal system-wide energy saving without consideration of the memory, as far as it is controlled by an SVCS CPU.We introduce an energy-optimal frequency assignment, for both an SVCS CPU and a synchronous NSVS memory, which optimizes the system-wide energy consumption. We derive the energy-optimal clock frequencies for an SVCS CPU and a synchronous NSVS memory, as a function of the number of processor clock cycles, the number of memory accesses and the hardware energy model. Our technique modifies the frequency assignment of the CPU and the memory used in previous DVS schemes, which ignore the memory energy. It enables the system-wide energy-optimal settings and achieves additional 50% energy reduction over previous DVS schemes. This technique can also be applicable to synchronous NSVS peripheral devices.