This paper proposes a class-C digitally controlled oscillator (DCO) using constantly-conducting NMOS biased switchable capacitor, aiming to optimize the off-state quality factor, reduce the off-state capacitance and improve the oscillator transient behavior. The DCO is fabricated in a 28 nm CMOS technology. With a unitary-weighted SC bank, the DCO shows an inherently monotonic tuning with a range of 8.2-11.1 GHz (30.1%), and a very fine tuning resolution of 40kHz. The class-C DCO achieves -115.5 dBc/Hz phase noise at 1 MHz offset from 10 GHz carrier frequency with 23 mW, resulting in a -182 dBc/Hz FoM and -191.5dBc/Hz FoMT.

This work presents a reference frequency and current generator circuit with high stability to temperature and process variations without requiring any post-fabrication trimming. The design serves as the reference generator in an active gate driver IC for Silicon Carbide transistors. It incorporates an 8MHz relaxation oscillator and a 12μA self-calibrating current reference. Both circuits share a parallel-connected discrete off-chip resistor and capacitor to eliminate the impact of on-chip process variations. A temperature stability of 45ppm/°C for the frequency and 54ppm/°C for the current is achieved by applying a closed-loop comparator error feedback as well as a resistor temperature compensation. The overall frequency and current standard deviation for process variations is 0.70% and 0.47%. The circuit is fabricated in a 0.18μm BCD technology.

This paper presents the design of a high-voltage (HV) single-inductor multiple-output (SIMO) fixed frequency DC-DC Buck converter for the power management unit of a Gate-Shaping digital gate driver for Silicon-Carbide power MOSFETs. Through shaping the switching waveform which drives the power MOSFET there are significant improvements regarding energy efficiency and electromagnetic compatibility achievable. Driving the gate of the power MOSFET the gate driver is provided with a galvanically isolated power supply of 20 V. Thus, the 0.4 W HV SIMO buck converter generates the internal 5 V and 1.8 V voltage rails required by the gate driver from the 20 V isolated power supply. It can provide up to 60 mA on each rail for analog and digital signal processing as well as driving the internal power MOSFETs. The design has been fabricated on an area of 0.6 mm2in a 0.18 µm HV BCD technology. In measurements it provides an average efficiency of 81.16 % over the whole operating range and a measured maximum efficiency of 87.44 %.

This work presents a novel zero-voltage-switching technique and demonstrates its feasibility in two exemplary DC-DC buck converters. The proposed system makes use of the nonlinearity of the reverse transfer capacitance to infer the voltage across the switch. The proposed method does not require additional expensive high-voltage components at the switch node, without resorting to bandwidth and voltage-limited high-voltage processes. The concept allows for full integration in low-cost, high-performance CMOS nodes, thereby enabling modern gate drivers with additional intelligent digital feature-sets to be used in HV environments. The technique is demonstrated to work using 650 V GaN and SiC switches across wide ranges of dead-times, regulating these from hundreds down to single nanoseconds.

This paper presents a low-noise low-dropout regulator (LNLDO) implemented in a 28 nm technology. The LNLDO features a two-stage architecture, using a low-pass filter with a very low cut-off frequency to separate the regulation loop and the noisy devices such as resistive divider and bandgap reference. Supplied by a 1.5 V-1.8 V input voltage, the LNLDO is able to provide a stable output voltage ranging from 0.73 V to 1.71 V, with a current supply ability from 0 to 35 mA. An on-chip capacitance enhancer is used to stabilize the regulation loop without an additional external capacitor. The RMS noise from 10 Hz to 100 kHz of the LNLDO is below 20μV.

This paper presents an approach for a system-level noise simulation in the frequency domain for RF systems. The noise analysis is able to depict frequency conversion due to nonlinear or time-varying circuits and can also consider the signal processing in the digital part. Therefore, it is possible to analyze the noise from all parts of the system at a point of choice, e.g. directly at the demodulator input. The approach is based on analog models of the genuine circuit level implementation used for system level exploration or verification purpose. It can be integrated in a conventional system level simulation with nearly no overhead. The noise analysis is implemented on top of an already existing event-driven RF simulation approach which uses a combination of System Verilog and C++ for modeling. MATLAB is used for post-processing and visualization of the results.

Nanoscale CMOS enables and forces the use of digital-centric RF architectures, where timing resolution is traded for analog resolution. Simultaneously, digital circuits act as aggressors endangering the performance of the time continuous digital and analog parts. The switching activities of logic cells result in power supply variations which lead to jitter in the digital signal paths and causes interferers coupling to the analog paths, appearing as e.g. phase noise, crosstalk, unwanted frequency conversion, etc. Since todays commonly used AMS simulation methods are limited to register-transfer level (RTL) models for the digital domain, the electrical behavior caused by digital switching is not considered. Here, a method for modeling logic cells with regard to power supply noise is presented using the available characterization data of a standard cell library. It covers the influence of switching on the supply voltage as well as influences of supply variations on the digital path delay and their feedthrough to blocks of the RF domain. A fast event-driven simulation of an entire AMS system regarding the mentioned aspects is enabled. The method is demonstrated on a digital-centric transmitter to detect the effects on system level.

An ultra low power CMOS voltage reference has been developed in a low-cost CMOS 130 nm technology. The design benefits in particular from using only one standard CMOS process without incorporating any resistors, op-amp, bipolar transistor or other CMOS processes. The circuit draws ultra low current of 230 nA from supply voltage of 1.2 V. The proposed circuit generates output an voltage of 698.5 mV with a temperature coefficient (TC) of 107ppm/°C in a range from 0 °C to 120 °C. It achieves superior coefficient of variation, σ/μ, of 0.79 % respect to other reported state-of-the-art solutions. It also features a very small size of 78.2 μm × 91 μm with an active area of 0.007 mm2.

Multistandard SoC's including advanced RF and analog circuitry with digital blocks are pervasive in modern IC's. However, the system design and verification methodologies that capture the complexity of multistandard RF SoC's are still limited. In this paper, an HDL design methodology is introduced for multistandard RF SoC's, which covers all the design layers from system design, to automatic extraction of the models from circuits and a systematic top level verification. The offered HDL based design methodology combines top down and bottom up design approaches, and brings the design and verification closer by reflecting the circuits to models automatically via an Automatic Parameter Extraction (APX) tool. System or block level verification is obtained with models automatically by overnight runs, without the need for extra test benches or designer interaction. This enables short term detection of functional errors or performance losses. A first time tape out of a multimode Bluetooth transceiver SoC is designed and fabricated in 8 months by using the offered methodology. The accuracy of the system level simulations show a very good match with the measurement results after fabrication. The test SoC is fabricated with 0.13 μm CMOS technology.

This paper describes a functional verification methodology for multi-standard wireless Systems-on-Chip (SoC) based on SystemC Virtual Prototyping (VP). The proposed semiautomatic pin-accurate RF VP generation method reduces huge handcrafting work to abstract circuitry into the event-driven simulation domain with satisfactory accuracy, while enabling the flexibility to choose different abstraction levels. A seamless transition between various signal abstractions is enabled by operator overload, e.g. passband and equivalent baseband in order to minimize simulation time according to test cases. This methodology is demonstrated for a low power RF transceiver with the achieved simulation speed of 500μs in 10s computation time.

Direct current measurement is one of the most important control characteristics for DC-DC converters. This sensitive method is used for current control of converters, which is much faster and more accurate than voltage control. Unfortunately, the sensitivity of the current measurement is also its major drawback. Especially in automotive applications, electromagnetic interference of the increasing number of electrical appliances severely degrade the performance of analog signal processing. Having proven to be more robust and error-prone, digital signal processing has to be preferred. This work presents a universal high-side current measurement at automotive battery voltage levels up to 24 V with direct analog-to-digital (A/D) conversion in a 180 nm technology. The A/D converter has been realized as 9 bit successive-approximation (SAR) ADC, with a sampling rate of 10 MS/s to detect DC-DC converter switching frequencies above 1 MHz. The combined circuit area of 0.2 mm2dissipated less than 2 mA at 1.8 V supply voltage. Simulation results of the extracted layout reflect the transient waveforms of a DC-DC LED driver during continuous and discontinuous conduction mode.

Photovoltaic (PV) energy harvesting suffers from output energy reduction due to shading, dirt accumulation or manufacturing variability. Typical PV modules consist of 60 solar cells connected in series. Hence, shading a single cell can cause a whole substring of 20 cells to be bypassed. To overcome these drawbacks, this paper proposes the application of boost converters on submodular level, cutting the series connection to only a few cells. System level simulations prove that this architecture features increased output energy compared to state-of-the-art approaches like power optimizers. For reducing component costs and increasing system reliability, an ASIC for this application has been developed in a 150nm CMOS technology. This paper describes the design and the implementation of a highly efficient hysteretic controlled boost converter. Its high switching frequency of more than 500 kHz enables operation on a single phase while achieving an RMS input current ripple of less than 1.5 % required in photovoltaic applications. Measurements prove a RMS current ripple of less than 1 % and a maximum switching frequnecy of 650 kHz.

This paper presents a low noise wearable wireless Electrocardiogram (ECG) system used for long term homecare and noninvasive monitoring three Leads ECG signals. An ac coupling circuit is implemented to remove the dc offset component created by the body movement and employs a high common mode rejection ratio (CMRR) instrumentation amplifier to reduce electromagnetic interference (EMI). The analog front end is connected to the End-Device which samples the three Leads signals with 200 Hz sampling frequency and sends data to a Coordinator on the PC using ZigBee protocol. A QRS and heart rate detection algorithm is implemented on a GUI data acquisition host. The system is evaluated when the body is walking and running. A reasonable performance is achieved even under body motion.

This paper presents a concept study on the monolithic integration of module-integrated converters for the application in grid-connected photovoltaic modules with output powers smaller than 10kW. Therefore three possible models on the basis of the actual grid requirements are developed and their characteristics are compared. These concepts use a boost converter on submodule level to improve the performance in mismatch situations. The boost converter is optimised considering different DC link voltages, areas and submodule numbers. An efficiency of 95.1% is achieved with four submodules and area requirements of 12mm2. In a comparison of the energy output under partial shading of all three concepts, it can be shown that a small number of submodules is advantageous for the energy output. It is shown that a solution with submodule converters and a module-integrated inverter has benefits for cost-effective integration and newer application scenarios.

This work presents a promising approach for driving multi-color RGBW high current LEDs for general lighting. Based on a DC input voltage, the applied topology correlates on a DC-DC flyback converter. Physical advantages in LED applications compared to resistive electrical load open room for elementary changes in the converter topology, which makes the presented work superior to state-of-the-art LED drivers in energy-efficiency, complexity, form-factor and cost. The presented capacitor-free single-inductor multiple-output LED driver offers multiple output voltages in order to gain high efficiency. Besides that, a single inductor is used to supply multiple outputs, without the necessity of capacitors. The presented work has been developed in a 0.18 μm technology. With a total output power of 6.5 W, the proposed LED driver light output is up to 600 lm, which is comparable to a standard 60 W light-bulb. The light output is related to a modern Retrofit LED lamp, but also has the enhancement of creating dimmable and tunable white colors.

LED based luminaires are capable of providing innovative functionalities, such as color control and color temperature adaption. In fact, precise control of these two parameters has turned out to be very complex and challenging. This paper presents an advanced control technique for a very accurate and robust adjustment of both color and color temperature. Additionally, the proposed methodology enables system optimization of a LED based luminaire regarding various parameters, e.g. maximum color rendering index (CRI). The control signals for any PWM-switched LED driver can be tuned accordingly by the system controller. The algorithm is tested in simulations for three different luminaire realizations, namely RGB-W, RGB-A and RGB-CAW. The CIEDE2000 color difference formula is applied for computing the perceivable color difference ΔE by the human eye. The developed color control algorithm achieves a superior minimization of the absolute color distance to ΔE ≤ 0.21, which is not even perceivable by the human eye. This performance can be realized over a wide color temperature range from 3200K to 7500 K while luminous output is kept constant. Due to the applied optimization, a CRI of ≥ 90 can be maintained over the same color temperature range for all three scenarios. Simultaneously, the deviation of correlated color temperature ΔCCT is minimized to less than 50 K, which is a precision of more than 98 %. The novel algorithm considers strict hardware limitations, such as finite switching speed or limited computation resolution, to account for implementations on an ASIC or a μC.

Photovoltaic applications require very small current and voltage ripples at the output of the solar cells to avoid power losses due to deviations from the maximum power point. Digital control offers optimization potentials to reduce this ripple without increasing the requirements on the analog-to-digital converters or the loop delay. This paper investigates the achievable current ripple reduction for two different digital current prediction algorithms applied to a hysteretic controlled photovoltaic submodule converter. A basic method relying on the continuity of the inductor current and an advanced algorithm, which compensates loop delay have been implemented in VHDL. Both methods are compared in structure and simulation results. The basic current prediction reduces the current ripple by 11 %, whereas the advanced current prediction decreases the ripple in total by 26 %. The whole controller including the advanced current prediction requires less than 0.1mm2in a 150nm CMOS technology.

This paper presents a continuous-time quadrature bandpass ΔΣ ADC that achieves 60dB DR and 67.4dB SFDR at 1MHz BW and 1MHz IF. The modulator uses capacitive feedforward architecture for the 3rdorder loop filter for reduced power consumption and a local feedback loop for optimized noise shaping within the required band. The design is targeted for low power low IF receivers and it achieves a total power consumption of 1.7mW from 1.2V supply. The chip is fabricated with UMC 0.13μm technology.

This paper presents a novel demodulator architecture which significantly improves the receiver performance for continuous phase modulation (CPM) signals with low-effort and low-complexity design. A Viterbi algorithm (VA) based soft decision is implemented with multiple bits differential discriminator to fully utilize the dynamical range. The whole digital circuit is verified and synthesized in ASICs, and its BER performance against channel noise is measured through FPGA with the Bluetooth receiver chip. Compared to hard-decision and decision feedback equalizer (DFE) methods, measurement results show that the proposed demodulator gains a large advantage in Bluetooth Low Energy (LE) communications where power efficiency and implementation complexity are of primary concern.

This paper presents a low complexity demodulator architecture which can significantly suppress the image interference in low IF receivers. Compared to other image rejection architectures, the power consumption and design complexity are greatly reduced. On the other hand, the multiplier free MUX based frequency shifter for baseband signal convertor and reference generator are implemented to highly reduce the calculation complexity. In addition, the symmetric LMS filter with single coefficient is used for the mismatch cancellation. Measurement results show the receiver using proposed technique gains significantly robustness against the image interference.

Maximum power point tracking (MPPT) techniques are widely applied in photovoltaic (PV) systems to fully utilize the PV array output power. Major challenges for MPPT are rapidly changing irradiance conditions and partial shading of the PV cells. These issues become even more severe for mobile applications, such as solar cells on the roof of electric vehicles. This paper deals with the implementation of a fast, fully integrated MPPT for a small number of solar cells connected in series with respect to mobile applications. For this special requirements, different open and closed loop MPPTs have been compared and evaluated. The optimal MPPT has hence been implemented. Furthermore, a bypass concept based on MOSFETs instead of bypass diodes is applied to utilize the maximum available power of the solar cells. The MPPT has been built in VHDL and realized in a 150nm CMOS technology. Due to its adaptive step size and its high sampling rate, the MPPT reaches the MPP within less than 0.65 ms with consumes less than 6.2 μW.

Capabilities of M-sequence radar front-ends have been shown in the past. For further system enhancement, specifications of constituent components can be re-aligned using system simulation. In this article, we want to present a system simulation setup for Agilent's Advanced Design System (ADS) which allows us to assess the impact of individual components on typical radar parameters. The latter characterize the performance of the overall system and it is their optimization which is targeted. For this purpose, new ADS stars, i.e. components for the (timed) synchronous dataflow (TSDF) simulator, have been implemented. Appropriate antenna models have been identified from literature and the signal deformations they impose are clearly visible from the simulated impulse response. Thus, simulations help to determine the antenna type suitable for the application. Due to the multiple signal domain simulation ability of ADS Ptolemy, it can be switched from a pure model based simulation to a transient-TSDF co-simulation during the design process. Using an appropriate channel model, such simulations provide a good estimate of real system performance right in advance to the actual component implementation and they help to keep track of real components agreement with the predicted behavior. Thus, a fair amount of flexibility is added in the design process compared to the former real-circuit component based approach.

This paper proposes a 2.4 GHz fractional-N frequency synthesizer based on a multiphase fractional frequency divider with a stepsize of 0.25. A retimer is implemented to remove glitches and improve robustness. The synthesizer fullfills the bluetooth specifications and consumes less than 5.8mW at 1.2V. In contrast to other structures, the proposed concept is simpler, duty cycle free, consumes less power, and operates at higher frequency.

In this paper, the design of biquad polyphase filters with capacitive crosscouplings is presented. Based on the elementary equation s rarr s - jomegac, which describes the frequency shifting, system theoretic modeling is used for design. Some important observations simplifying the design process are denoted. The developed structures have been simulated in Cadence using operational amplifier models with adjustable gain and bandwidth. Results are compared to those of a Tow-Thomas polyphase filter with comparable sum capacitance but with an operational amplifier amount twice as high. By limiting the gain bandwidth product of the models to reasonable values it is shown that operational amplifier performance does not need to be improved and hence a reduced power consumption can be expected.

Two LNA topologies for use in UWB systems are examined and compared in this paper. Design specifications have been derived from a ground penetrating radar system which is the target application. Circuits have been designed to cover the frequency range from 3.1 GHz to 10.6 GHz. The SiGe:C technology SGB25V of IHP Microelectronics is applied to enable volume production at low prices. For measurement purposes, input and output are matched to 50 Omega.

Since the design and realization of a complex system on a chip is error prone, functional verification should have been a main task in today's design flows but is still underestimated. This paper gives an overview of current modeling approaches to handle functional verification of a design on the top level, prior to tape out. The problems that arise from the different approaches such as baseband modeling and event-driven modeling are explained, and the resulting effects on the simulated system specifications are presented. The necessity of the approaches for future systems, which are not simulatable with current methods, is presented, and the needed extensions of the hardware description languages and simulators are proposed.