VITAL is a program for generating fully automatic layouts of any design that combines standard cells and macrocells. Among the program's unique standard cell placement algorithms are simultaneous X/Y placement and channel-density improvement algorithms and an innovative algorithm for reducing chip width by using over-the-cell crossover. Iterative cell placement improvement strategies, such as cell row balancing and cell migration, which result in over 10% area reduction, make VITAL an extremely effective layout tool. The frequent interaction of the placement algorithms with the routing function results in denser chip layouts, as much as 25% smaller than those achieved with commercial tools. The steps of the standard cell-placement procedure are described in detail.>

This paper describes a unique fully automatic chip compiler, HAPPI, that uses double-level-metal technology and 3 levels of interconnection to realize high-speed and maximum-density chip designs consisting of a varying mixture of custom and standard-cell macros within a chip topology that guarantees 100% signal and power routing. A heuristic technique for generating placements of “soft macros” that are balanced in both area and connectivity has been presented. A routing approach that uses three level interconnection to guarantee 100% signal routing at no more than maximum density +1 tracks for channels is described, as well as a method for distributing power inside the chip in two-level metal. Finally, results of chip design using the HAPPI compiler have been presented.

This paper describes a program for automatically computing the delay through LSI/VLSI chips which have been laid out using automatic layout programs. A unique algoristhm for synthesizing RC networks from artwork data, which significantly reduces execution time and computer storage, is included. A novel and simple method for determining the delay through logic gates due to arbitrary RC network load at the output is also presented and discussed.