Computation-in-Memory (CIM) has emerged as a promising solution to the memory bottleneck in data-intensive applications and AI accelerators; however, it introduces new testing challenges due to multi-row access patterns and higher sensitivity to variations. These challenges can cause marginal bitcells to fail under CIM operation even if they pass standard March tests, making existing approaches insufficient for ensuring reliable CIM operation. In this work, we propose March-CIM, a modified March test optimized for SRAM-based CIM, which overcomes this limitation. By using read current profiling and a trim-assisted sensing mechanism, our method identifies marginal bitcells that conventional tests miss and selectively subjects them to exhaustive CIM testing to verify their fault-free functionality. This method significantly reduces test time (and thus test cost) by eliminating unnecessary tests for the bitcells with reliable performance. We demonstrate the effectiveness of our CIM test approach using 22 nm FDSOI technology and confirm its compatibility with industrial memory built-in self-test (MBIST) tools with minor modifications, achieving a reduction of up to 67% in test time compared to exhaustive CIM testing. Our method is applicable for field testing to ensure reliable operation through periodically profiling bitcell behavior through MBIST under real-time infield conditions.

Today’s logic chips and System-on-Chips (SoCs) are ever-growing in size, complexity, and integration density. This drives a continuous need to develop novel and advanced ways to efficiently test such devices after manufacturing. High-bandwidth IJTAG over SSN (HB-IJTAG) is one such innovation that leverages the high-speed and parallel Streaming Scan Network (SSN) bus to concurrently access many local IEEE 1687 (IJTAG) networks.However, every time the high-bandwidth IJTAG access mode is activated, it must first be configured through the global IJTAG network. The initial configuration and subsequent reconfigurations constitute a substantial test time overhead due to the lower shift speed and serial nature of global IJTAG.This paper introduces wide-ranging enhancements to the high-bandwidth IJTAG access to allow for persistent utilization of the high-speed SSN bus. By eliminating the reasons for the expensive reconfigurations, high-bandwidth IJTAG can remain active throughout the entire test session. This results in a significant reduction of test setup time and more efficient test delivery. Our experiments clearly demonstrate these benefits in different pattern delivery scenarios. Persistently using the high-bandwidth data delivery reduced the relevant IJTAG pattern execution time by up to 243x, yielding an up to 18x lower overall test time for SSN ATPG patterns.

The increasing complexity of Integrated Circuits (ICs) is driven by heterogeneous functionality and stringent performance demands. This necessitates scalable and efficient design for testability (DFT) solutions to ensure cost-effective test access and functional correctness. Streaming Scan Network (SSN) and High-Bandwidth IJTAG over SSN (HB-IJTAG) enhance the test efficiency significantly by accelerating the data transfer and optimizing the test execution. However, these technologies introduce validation challenges due to more intricate control mechanisms and their large-scale deployment.This paper presents a novel, holistic approach for generating and sequencing functional validation patterns. These patterns systematically leverage SSN and HB-IJTAG capabilities to optimize overall efficiency. The proposed methodology enables the concurrent and robust validation of hundreds of SSN and HB-IJTAG DFT components, significantly improving the overall test execution time.

Adherence to the ISO 26262 standard requires periodic testing of embedded memories in automobiles, which must be completed within short time windows during normal vehicle operation. This testing must preserve memory contents post-test and integrate test logic seamlessly with system functionality, all while minimizing disruption to vehicle performance. This paper proposes a Memory Built-In Self-Test (MBIST) architecture that addresses these challenges by using a series of short test bursts. The architecture dynamically adjusts the length of each burst based on available memory idle time, ensuring efficient testing without interfering with critical system functions. Additionally, the architecture minimizes hardware overhead by reusing existing resources and introduces a direct access interface for tighter integration with system logic, further enhancing test efficiency and reducing latency.

IEEE Std P3405 is a new standardization activity under the umbrella of TTTC’s Test Technology Standardization Committee (TTSC). In 2023, a Study Group formulated a Project Authorization Request (PAR), which was approved and since December 1, 2023, the P3405 Working Group is active under elected chair Sreejit Chakravarty. This standardization activity focuses exclusively on the test and repair of chiplets’ inter-die interconnects. In the PAR, the scope of the activity is described as follows. "Chiplet-based designs contain dies using proprietary interconnect technology. These dies might come from multiple design groups. Inter-chiplet interconnects are dense, large in number, and prone to manufacturing defects. For cost-effective chiplet packaging, an effective and efficient mechanism to test and repair chiplet interconnects is required. The chiplet interconnect test and repair infrastructure is spread across chiplets and designed by multiple design groups, necessitating the need for a standard for chiplet interconnect test and repair. The purpose of IEEE Std P3405 is to enable interoperability of interconnect test and repair infrastructure of chiplets from multiple design groups. Chiplet-based designs involve multiple parties: Chiplet Maker(s), Packagers, and End User(s). Features supporting the test and repair of chiplet interconnects are part of individual chiplets, which are implemented by individual Chiplet Makers. These features are needed to serve the Chiplet Makers’ (prepackaging), Packagers’, and End Users’ test and repair objectives." In this special session, a handful prominent members of the Working Group express their personal views on the outcome of the standardization work. The views expressed are from the authors alone and do not necessarily align with the view of the IEEE Std P3405 Working Group.

As PDL has been developed to be syntactically compatible with TCL, it is possible to use an interpreter to enhance test routines with programming features, such as variables, flow control, etc.. Moreover, one of the big novelties of IEEE 1687 is the native support of interactive behaviour thanks to the PDL-1 instruction set. which allows data read from the target system to be returned to TCL Interpreter. However, it is not quite clear what “Interactive behaviour” actually means and how it gets from simulation to automatic test equipment. IEEE 1687 is a “descriptive” standard, so there is no provision or limitation on the way the test routines will be executed and if and how they will interact with the System Under Test.

Error Correction Codes (ECC) in current designs typically serve two purposes. For emerging non-volatile memory types (NVM), such as embedded magnetoresistive random access memory (eMRAM), ECC is necessary to counter the probabilistic behavior of the NVM, rendering the combined NVM/ECC a deterministic memory again. The second and much more prominent usage of ECC today is to protect the system against transient faults in the memory, here typically for SRAMs. On the other hand, new defect types for such emerging memories and new technology nodes may exceed reasonable costs of conventional row and column repair. To improve yield, users explore ECC as an option to augment the repair capability of the memory. This paper brings such an augmentation into a standard memory test and repair flow. It allows a user-defined, post silicon trade-off of using all or parts of the corrective power of the ECC for yield improvements and/or for system protection. Experimental results underline the very low area cost of this augmentation.

Magnetoresistive random access memory (MRAM) is an attractive option to replace eFlash. The recent demonstration of a nano-second write speed and a 10e14 endurance are compelling performances even as an embedded MRAM for cache replacement. Both eFlash and cache applications often use large array sizes, which require tight defect control. The unique defects in MRAMs that are not easily detectable with traditional memory test algorithms can potentially cause test escapes. Test escapes will not only delay the manufacturing process but also cause reliability issues, which is fatal for safety-critical applications such as automotive. This paper presents effective ways of screening hard-to-find defects related to oxide surface quality. The devices with minor oxide degradation have properties in the grey zone, which spec out some of the properties, although they pass the functional test. We introduce a new test method to screen those spec out cells using read reference trimming.

As Systems-on-Chip (SOC) designs grow in complexity, so do the challenges associated with testing them. Some of the obstacles SOC designers face include limited I/O and scan channels, routing and timing closure issues, increasing manufacturing test and defect diagnosis time, and growing test data volume. Various design-for-test (DFT) techniques exist to handle complex SOC designs that have multiple cores. One new DFT implementation technique is the streaming scan network (SSN) high-bandwidth parallel data bus. SSN addresses many of the SOC challenges by providing an optimized packet-based scan data delivery system. It also dynamically optimizes test time by adjusting the data applied to each core. However, SSN is limited to delivering scan data; it cannot be used to deliver data to individual instruments in a physical block using the IEEE 1687 (IJTAG) network. This paper introduces a new high-bandwidth IJTAG DFT technology that leverages the existing high-speed parallel SSN bus to drive the serial IJTAG network. It describes the DFT implementation methodology, the impact to the backend in terms of timing and SDC, and how verification was done by Intel as they deployed it on multiple dielets in their next generation client CPU. Moreover, data on area overhead and the overall test cost savings achieved is presented.

In multi-die systems, interconnect clusters on chiplets are arranged in bump array patterns, and testing these interconnects for defects like shorts and opens is crucial for ensuring communication among different dies. Various ATPG algorithms have been developed to cover these defects. This paper introduces a fully automated EDA tool flow that utilizes the 3Dblox Open Standard to extract the physical location of interconnects and generate physical-aware test patterns. This optimized approach ensures comprehensive testing of all critical D2D interconnects, essential for a defect-free 3DIC system.

Scaling down the transistor size enables a cost-effective high-performing solution in modern semiconductor designs. However, the added complexity of process and extremely small critical three-dimensional spacing of the transistor structure make it more challenging to maintain precise variation control. Defects introduced here can lead to different intermittent behaviors, some of which might not appear as fails during traditional testing procedures but might manifest as a system failure in the field. The emergence of artificial intelligence chip design has introduced high demands for a massive number of multi-cores connected in parallel with a huge memory array size in a chip. This further increases the importance of identifying rare tail events through in-depth diagnosis in advanced nodes. Various sophisticated algorithms have been proposed to improve defect coverage. However, the addition of algorithms may increase test cost tremendously while providing limited benefits for specific fault types which may not happen. Therefore, selecting a smart combination of algorithms that provide enough coverage for the specific product application is essential for cost-effective testing. In this paper, we review the electrical properties of marginal defects inserted in an SRAM device to evaluate test escapes in the latest technology. We also present a new algorithm to improve test coverage efficiency. A commercially available memory BIST tool was used to load a DFT compatible algorithm and operation set for memory test. A commercially available analog simulation tool was used in combination with a novel defect simulation flow to evaluate digital and analog behavior of the device.

Testing magnetoresistive random access memory (MRAM) presents several challenges, particularly in scaled technology nodes. One major challenge is the increased interconnect resistance from the bitline and sourceline, which leads to issues like the near-far effect, where bitcells farther from the sensing circuit exhibit higher resistance. Additionally, the fabrication process can result in defects that may not be easily detectable using conventional testing methods. Another factor that makes the screening process more difficult is the presence of process variation. This paper proposes a memory-built-in self-test (MBIST) compatible method that compensates for the interconnect resistance effect using multi-level references and memory partitioning. In addition, the proposed method aims to find the location in the memory array that is less affected by process variation and use it to adjust the screening boundaries for the entire memory to detect defective bitcells more effectively. On average, the proposed method shows around 50% defect coverage improvement and 76% weak bitcell coverage improvement over its previous counterparts. The detected defects will be further evaluated for repair by ECC or other redundancy schemes to maximize product quality and yield.

As technology scales down, the interconnect parasitic resistance more dominantly affects performance degradation and test escapes. The wire resistance increase is especially a great challenge in resistive-based non-volatile memories (NVM) such as magnetic random access memory (MRAM) and resistive RAM (ReRAM) because it can cause faulty reading of the data. The resistive-based NVMs perform the read operation by sensing the bitcell resistance relative to a reference value. Therefore, additive parasitic resistances along the read path, including the bitline (BL) and sourceline (SL) resistances, may cause incorrect read operation. The additive path resistance also makes defect screening harder. A defect screening method designed to detect faulty bitcells located near the sensing circuit may not effectively screen out a bitcell located far from the sensing circuit with the same defectivity level and lead to test escapes. Utilizing a multi-level reference, the proposed new testing scheme compensates for the additive line resistance effect and improves coverage for local defect screening. The detected fault will be further evaluated for correction by ECC or repaired to maximize field coverage. The proposed method is applicable to existing industrial memory built-in self-test (MBIST) solutions with minor modifications.

From the Project Authorization Request (PAR) of IEEE Std P3405: “Chiplet-based designs contain dies using proprietary interconnect technology. These dies might come from multiple design groups. Inter-chiplet interconnects are dense, large in number, and prone to manufacturing defects. For cost-effective chiplet packaging, an effective and efficient mechanism to test and repair chiplet interconnects is required. The chiplet interconnect test and repair infrastructure is spread across chiplets and designed by multiple design groups, necessitating the need for a standard for chiplet interconnect test and repair. The purpose of IEEE Std P3405 is to enable interoperability of interconnect test and repair infrastructure of chiplets from multiple design groups. Chiplet-based designs involve multiple parties: Chiplet Maker(s), Packagers, and End User(s). Features supporting the test and repair of chiplet interconnects are part of individual chiplets, which are implemented by individual Chiplet Makers. These features are needed to serve the Chiplet Makers’ (pre-packaging), Packagers’, and End Users’ test and repair objectives.”

As we move toward the commercialization of Spin-Transfer Torque Magnetic Random Access Memories (STT -MRAM), cost-effective testing and in-field reliability have become more prominent. Among STT-MRAM manufacturing defects, pinholes are one of the important ones. Pinholes are defects on the surface of the oxide layer which degrade the resistive values and, in some cases, cause an oxide breakdown. Some moderate levels of pinhole defects can remain undetected during standard functional tests and may cause a field failure. A stress test of the whole memory, including multiple cycles of long writes, has been suggested to detect candidate pinhole defects. However, this test not only causes extra costs but also degrades the reliability of MRAM for the entire array. In this paper, we have statistically studied the behavior of pinholes and proposed a cost-effective testing scheme to capture pinhole defects and increase the reliability of the end product. Our method limits the number of test candidate cells that need to be hammered, providing a reduced test time of up to 96.42% for our case studies compared to existing methods. This is while the advantages of standard tests are all preserved with our method. The proposed approach is compatible with memory-built-in self-test (MBIST) schemes.

Embedded non-volatile RAM technology, and in particular Magneto-resistive RAM (MRAM), continues making great progress in read/write speed and cycling endurance, now rivaling traditional memory technologies. This advancement together with their low-energy consumption and non-volatility opens huge application markets. While stand-alone MRAM products are already being deployed, the first pilot applications for embedded MRAM are just starting to emerge. The availability of Design-for-Test (DFT) tools is key in the transition from low-volume technology exploration and pilot projects to high-volume production. In this paper we explore a new aspect of a Memory Built-In Self-Test (MBIST) tool for eMRAM, namely Error Correcting Code (ECC)-aware test and repair technology. This new MBIST capability provides the ability to make in-system, user-programmable trade-offs concerning the eMRAM repair resources. Having extra control over the repair resources in turn increases both manufacturing yield as well as the longevity of the product in its application.

Following IEEE Standard Association (IEEE SA) guidelines, actively used standards should be revised every ten years. IEEE 1149.1 was published in 2013, while IEEE 1687 was published in 2014. Hence, both standards were revisited, and for both, it was determined that a refresh would be beneficial to the community. Consequently, working groups were established and are ongoing. Here, we outline their agenda and progress. Since 2014, other standards that based on 1687 were initiated. In this paper IEEE P1687.1, IEEE P1687.2, and P2654 report on their progress. An in-depth update of IEEE P1687.1 was given during the International Test Conference (ITC) in 2022.

Modern integrated circuits used in automotive, industrial, consumer, and IoT (Internet of Things) applications often have limited pin counts. Despite this, these devices can be complex, with significant digital and analog content. These features require rigorous testing to address the quality and reliability requirements of these applications. Because of their limited pin count, a TAP controller interface is often not an option or the TAP controller interface itself may not be an option for other reasons, such as die area. Further, the increasing number of IP based designs, along with the increasing availability of IP cores can result in an IP being integrated deep inside a design. Designers, DfT engineers, and test engineers are facing increasing challenges with the integration and testability of IP in their chips. They also have the task of having to test through interfaces that may change depending on the needs of the customers. IEEE P1687.1 is working on processes that will provide a means for automating communications through non-TAP interfaces, making these types of products ideally suited for the techniques currently under consideration for standardization. This paper, reviews the latest topics being discussed by the working group, including the framework for communicating through these interfaces. It discusses how proto buffers (protobufs) can be used to help bridge the gap between a host controller, like an ATE, and an IJTAG network. The approach leverages the concept of Remote Procedural Calls (RPCs) from the IT space and the integer bit vector (intbv) concept from myHDL to support communications through interfaces and between subroutines handling retargeting and handling control of the interface. A model is presented for evaluating the options and various criteria are reviewed with respect to the framework. The paper also explores debug concerns and potential security issues and how those can be addressed.

Spin-Transfer-Torque Random Access Memories (STT-MRAM) offer attractive features such as high-density, low power consumption and non-volatility. Process variations (PV) are one of the critical problems during the manufacturing process. To mitigate PV, reference trimming is used, to compensate for the offset of the tested array based on their functional behavior. However, additional tests can increase the manufacturing test budget. In this paper, we present a novel approach based on address skipping during the trim search step of the memory test, by accessing only a small sub-array. This enables a significant reduction in trim search time. We perform a progressive skip test flow to improve the overall test time for binary search based trim search by up to 29% while ensuring to capture any failing bits with our proposed skip search.

Spin-transfer torque magnetoresistive random-access memories (STT-MRAMs) are gradually superseding conventional SRAMs as last-level cache in System-on-Chip designs. Their manufacturing process includes trimming a reference resistance in STT-MRAM modules to reliably determine the logic values of 0 and 1 during read operations. Typically, an on-chip trimming routine consists of multiple runs of a test algorithm with different settings of a trimming port. It may inherently produce a large number of mismatches. Diagnosis of such a sizeable volume of errors by means of existing memory built-in self-test (MBIST) schemes is either infeasible or a time-consuming and expensive process. In this paper, we propose a new memory fault diagnosis scheme capable of handling STT-MRAM-specific error rates in an efficient manner. It relies on a convolutional reduction of memory outputs and continuous shifting of the resultant data to a tester through a few output channels that are typically available in designs using an on-chip test compression technology, such as the embedded deterministic test. It is shown that processing the STT-MRAM output by using a convolutional compactor is a preferable solution for this type of applications, as it provides a high diagnostic resolution while incurring a low hardware overhead over traditional MBIST logic.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the most promising candidates to replace conventional embedded memory such as Static RAM and Dynamic RAM. However, due to the small on/off ratio of MRAM cells, process variations may reduce the operating margin of a chip. Reference trimming was suggested as one of the ways to reduce variation impact to the chip. In addition to process variation, thermal variations reduce the operating margin of STT-MRAM even further and impose a tighter limit on the operating temperature range than CMOS technology. Defects that relate to marginal thermally behavior are especially difficult, because it is very costly to test across the entire operating temperature range at the tester, and can even reduce the lifetime of the chip. Therefore, we propose a Memory Built-in Self Test (MBIST) supported screening method to accurately predict the failure behavior of a device under test at high temperatures solely from lower temperature test. By adding five more BIST runs at 85°C, we are able to predict MRAM failures at 125°C with 99.11% accuracy. This prediction can then be used to define a reference trim adjust value to optimize the read operation across the entire operating temperature range of the MRAM.

The industry is moving forward with non-TAP, chip-level interfaces driving IEEE 1687-2014 networks. Recent literature not only describes such interfaces, like I2C and IEEE 1149.7 variants, but also demonstrates that such interfaces to IEEE 1687 are already proven in silicon. Common to those implementations is the need for "private" extensions of IEEE 1687 to make it support non-TAP interfaces. The goal of IEEE P1687.1 is to directly support non-TAP interfaces. In this work, we summarize the thought progression from IEEE 1687's data register callbacks to IEEE P1687.1's transfer function, which allows alignment with IEEE P2654, and possibly IEEE P1687.2.

This paper introduces a standards-based framework which enables two types of test re-use: direct re-use of test patterns written for low-level components of a system, and access by high-level tests of test features embedded within the low-level components. The underlying mechanism for both is the encapsulation, retargeting, and transformation of test procedures through successive layers of hardware interfaces, as codified in two standards being developed by IEEE Working Groups (P1687.1 and P2654). Examples demonstrate the steps in the process and illustrate both the challenges and opportunities of this approach.

eMRAM (embedded Magnetoresistive Random Access Memory) is an attractive solution in many non-volatile memory applications because of its small size, fast operation speed, and good endurance. However, due to a relatively small on/off resistance separation, it is a challenge to set an optimal reference resistance to reliably differentiate between a read memory data “1” and “0”. Several trimming circuits are described in the literature to finely adjust a reference resistance value. These circuits are controlled from chip inputs causing time-consuming tests and off-chip engineering analysis. This paper presents a fully automated on-chip trimming process leveraging existing memory BIST (Built-In Self-Test) resources. It analyzes a massive amount of array property data with a minimal number of tests and optimizes the reference trim settings on-chip without the need for any external intervention.

IEEE 1687 (IJTAG) provides significant value to the DFT engineer and efficiency in the DFT flow. However, IJTAG requires 4 or 5 pins to drive an IEEE 1149.1 compliant TAP controller. Many of our designs have fewer than 4 pins total, prohibiting the usage of IJTAG. In this paper we describe a solution that drives an embedded TAP controller from a chip interface that consists of only 2 ports, a clock port and a bidirectional data port. The embedded TAP then drives the IJTAG network as usual, providing us all the benefits of IJTAG. To enable this, we needed to expand the used EDA tool's IJTAG support in the direction of IEEE P1687.1. Experiences from the implementation of this solution in a productive chip show significant productivity gains.

Many modern devices have a very limited number of digital pins, yet they are often quite complicated internally. These ICs can't afford the luxury of a traditional JTAG TAP controller and the associated 4 or 5 extra pins. Nonetheless, these devices often contain significant digital and analog content. This complexity makes testing very challenging. Moreover, IP-based design often results in having an instrument buried deep inside a device, the access of which requires transitioning through multiple interfaces and controllers. This is exactly the situation DfT and test engineers face when designing and implementing tests for embedded IP. Techniques proposed for IEEE P1687.1 enable an automated mechanism for retargeting tests through a variety of non-TAP interfaces. This makes these products ideal candidates for IJTAG and IJTAG.1 test strategies. In this paper, we focus on demonstrating how on-chip test functions and IP can be successfully controlled and observed through non-TAP interfaces by controlling data flow using RVF (Relocatable Vector Format) and callbacks. This unique and novel approach ensures tool interoperability and allows tools to model interfaces in the same way, without requiring special descriptions for each one. The paper proposes an automated tool flow for retargeting the tests and provides example implementations on several specialized designs including I2C, an In-System TAP, IEEE 1149.7like interface, and a security block.

Complex application specific SoC are being developed for hardware support artificial intelligence (AI) applications. Such a complex SoCs are integrating a large number of on-chip and off-chip memories, numerous cores and interfaces including in our case a hierarchy of embedded TAPs, as well as security measures and Design-For-Test (DFT) structures. In this case-study paper, we demonstrate using IEEE 1687-2014 (IJTAG) to integrate all these different components into a single, unifying methodology. From this, we derive the benefits of workflow efficiency and fast silicon bring-up. For example, we can report that silicon bring-up of the DFT of the entire SoC was completed in about 4 days, and other bring-up aspects of the Soc were also completed in very little time.

eMRAM (embedded Magnetoresistive Random Access Memory) has many attractive properties such as small size, fast operation speed, and good endurance. However, MRAM has a relatively small TMR (Tunneling Magnetoresistance) ratio, which means a small on-off state separation. It is a challenge to set an optimal reference resistance to reliably differentiate “1” and “0” states. Several trimming circuits were suggested in the literature to adjust a reference value and its search range. The trim setting can be controlled manually by user input; however, it consumes huge test time and requires off-chip engineering analysis to search and apply a trim setting for an individual memory array. In this paper, we will discuss the recent silicon results of fully automated trim process leveraging existing MBIST (Memory Built-in Self-Test) resources and new features to accommodate more complicated multi-step reference setting implementation through minor update of an existing MBIST circuit. The proposed MBIST solution uses a minimal number of tests to analyze massive array properties and automatically set complicated multi-step trim settings within a chip without the need for an external tester or manual adjustments.

A tile based design methodology consists of developing design blocks that are inserted in design layouts by placing blocks next to each other, making a tile-to-tile connection by abutting corresponding physical signal lines at the border of the tile. Very large systems can be easily and rapidly developed by seamlessly integrating tile elements in the layout. Further, the ease of top-level integration underlines the advantages over a bottom-up approach. However, this tile-based approach is incompatible with traditional DFT tools, which were created to work in accordance with the bottom-up design methodology. This paper outlines some of the obstacles to overcome, to support a truly tile-based DFT methodology. We describe here a working solution for a large production design, underlining a successful implementation of a tile-based Memory Test methodology.

In this IP session, there will be 3 presentations focusing on the state-of-the-art memory test practices from tools and industrial implementation perspectives. The 1stpresentation will discuss the memory test strategies in the automotive space. The 2ndpresentation discusses memory tests strategies for enabling test cost reduction. The 3rdpresentation will discuss on array BIST and its presence and usage in various applications of the current generation designs.

Content Addressable Memories (CAMs) have found widespread use in applications that require high speed search capabilities. Each cell in the CAM array is associated with a storage unit and a comparator logic. Due to the various customized features in the CAM implementations, creation of an automated BIST solution for testing them has presented unique challenges. This paper shows that, with suitable modifications to the CAM test collar, an existing BIST solution and flow traditionally used to test embedded SRAMs can be used to test the CAMs.

IEEE 1149.1-based top-level access to IEEE 1500-compliant IP cores is commonly used in industrial designs as the underlying infrastructure to provide test access, control, instrumentation, and ease of use. Validating the test infrastructure and its usage in the early design stages is critical to the success of the project. The new Internal Joint Test Action Group (IJTAG or IEEE 1687-2014) standard is a valuable component of this test infrastructure and is designed to promote efficient embedded instrument access. This paper describes one of first comprehensive applications of an IJTAG-based method to a state-of-the-art server microprocessor design from specification to production. We leveraged IJTAG to automate design modeling, enable faster and more advanced verification, and optimize manufacturing test access. In this work, we demonstrate a very high degree of optimization and automation, which is cost-efficiently enabled by IJTAG, and goes beyond the capabilities of typical in-house IJTAG-like system, currently in use in industry.

This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs, including FinFET technologies. We present results from a defect-oriented CAT fault model generation for 1,940 standard library cells, as well as the application of CAT to several industrial designs. We present high volume production test results from a 32 nm notebook processor and from a 350 nm automotive design, including the achieved defect rate reduction in defective-parts-per-million. We also present CAT diagnosis and physical failure analysis results from one failing part and give an outlook for using the functionality for quickly ramping up the yield in advanced technology nodes.

This paper focuses on an industrial application of the proposed 1687 standard to significantly improve the test development effort and quality of test patterns for mixed signal IPs of an automotive design. The P1687 standard will enable the industry to develop test patterns for IPs on the IP level without having to know how the IP will be embedded within different designs. To measure the impact of P1687, we are applying a commercial P1687 EDA tool on an industrial 65nm automotive design. The presented results underline the significant advantages of P1687 over the current IEEE Std 1149.1-based test methodology, in both, automation of test pattern development as well as reduction of test setup data volume by more than 50%.

As chips are getting increasingly complex, there is no surprise to find more and more built-in DFX. This built-in DFT is obviously beneficial for chip/silicon DFX engineers; however, board/system level DFX engineers often have limited access to the build in DFX features. There is currently an increasing demand from board/system level DFX engineers to reuse chip/silicon DFX at board/system level. This special session will discuss: What chip access is needed for board-level for test and diagnosis? How to accomplish the access? Will IEEE P1687 and IEEE 1149.1 solve these problems?

We present a flow to extract, simulate and generate test patterns for interconnect open defects. In contrast to previous work, the accuracy of defect modeling is improved by taking the thresholds of logic gates as well as noise margins into account. Efficient fault simulation is enabled by employing an aggressive fault collapsing strategy and an optimized fault list ordering heuristic which allows to combine the advantages of event-driven simulation with bit parallelism. Test generation complexity is kept in check by generating patterns for technology-independent segment-stuck-at faults first, thus reducing (though not completely eliminating) the need for sophisticated technology-aware test generation. Moreover, a comprehensive untestability analysis identifies new classes of untestable faults. Experimental results demonstrate high efficiency of the new flow, outperforming earlier work by two orders of magnitude.

Yield enhancements in the manufacturing process today require an expensive, long and tedious physical failure analysis process to identify the root cause. In this paper we present Axiom, a new technique geared towards efficiently identifying a single dominant defect mechanism (for example in an excursion wafer) by analyzing fail data collected from the production test environment. Axiom utilizes statistical hypothesis testing in a novel way to analyze logic diagnosis data along with information on physical features in the design layout and reliably identify the dominant cause for yield loss. This new methodology was validated by applying it to a single excursion wafer produced on a 90 nm process, in which the dominant failing physical feature was correctly identified.

We present a fully automated flow to generate test patterns for interconnect open defects. Both inter-layer opens (open- via defects) and arbitrary intra-layer opens can be targeted. An aggressor-victim model used in industry is employed to describe the electrical behavior of the open defect. The flow is implemented using standard commercial tools for parameter extraction (PEX) and test generation (ATPG). A highly optimized branch-and bound algorithm to determine the values to be assigned to the aggressor lines is used to reduce both the ATPG efforts and the number of aborts. The resulting test sets are smaller and achieve a higher defect coverage than stuck-at n-detection test sets, and are robust against process variations.

As technologies move below 130nm, the IC industry has seen a significant change in defect type encountered. Feature-related defects are becoming more prevalent than particle-driven defects in nanometer designs. The process and design variances require checks for the design-for-manufacturing (DFM) issues in order to achieve a high yield. Scan diagnosis targeted for the nanometer designs can provide quick, accurate and reliable failure information from the production environment. The ranked, fault classified and physically linked scan diagnosis results can, in turn, provide the guides for DFM checks. High volume diagnosis provides data to yield management system for statistical analysis. This presentation briefly explains the technology behind the scene, discusses scan diagnosis applications and shows the results.

A novel statistical learning algorithm is proposed to accurately analyze volume diagnosis results. This algorithm effectively overcomes the inherent ambiguities in logic diagnosis, to produce accurate feature failure probabilities, which are critical in understanding systematic yield limiters. The results of Monte-Carlo simulation are presented, which demonstrate the feasibility and impacts of various factors on this approach. Additional experiments based on injected defects are performed, which confirm the ability of this approach to generate accurate feature failure probabilities for an industrial design using actual diagnosis results.

This paper presents an extensive study on evaluating the effects of static alternative fault models (AFM) on product quality in the face of the latest defect screening techniques. The fault models that are presented in this research are multiple-detect stuck-at, static transition fault, and layout-based deterministic bridges. The results show the quality impact when these new fault models are combined with a high quality stuck-at and TDF test sets

This paper presents a flow for using logic diagnosis to turn production material into vehicles for yield learning. High throughput logic diagnosis is combined with the newly emerging field of design for manufacturing to enable layout aware diagnosis. The ability of the flow to calculate feature failure rates and the application of the failure rates for yield learning is demonstrated through volume data analysis on a production ASIC

Transition delay fault (TDF) testing has become a necessary test method in very deep sub micron (VDSM) technologies due to the presence of resistive defects that cause subtle timing failures. The transition delay fault model is based on a slow-to-rise and slow-to-fall fault at each node in the circuit. Some resistive defects such as resistive vias actually induce both faults and the TDF test set can contain unnecessary test patterns for proper screening of this type of defect. The inline resistance fault (IRF) model more accurately represents this defect type and is studied in depth in This work. ATPG experimental results show that IRF patterns can be generated 1.4 to 1.8 times faster with 45% to 58% fewer patterns than traditional TDF patterns. IRF and TDF pattern test results are presented and show that the more expensive TDF remains a more comprehensive test than IRF as expected, but that the quality impact of using only the IRF test set is minimal, especially when combined with effective IDDQ outlier screening such as statistical post processing. Additionally, a methodology is presented for the determination of the number of delay defects that behave according to each model from the test data alone, which is necessary to accurately determine delay defect coverage from multiple test coverage metrics.

A symbolic fault simulator is integrated in a Genetic Algorithm (GA) environment to perform Automatic Test Pattern Generation (ATPG) for synchronous sequential circuits. In a two phase algorithm, test length and fault coverage as well are optimized. However, there are circuits with bad random testability properties, that are also hard to test using genetically optimized test patterns. Thus, deterministic aspects are included in the GA environment to improve fault coverage. Experiments demonstrate that tests with higher fault coverages and considerably shorter test sequences than in previously presented approaches are obtained.

Until recently verifying multipliers with formal methods was not feasible, even for small input word sizes. About two years ago, a new data structure, called Multiplicative Binary Moment Diagram (*BMD), was introduced for representing arithmetic functions over Boolean variables. Based on this data structure, methods were proposed by which verification of multipliers with input word sizes of up to 256 bits became feasible. Only experimental data has been provided for these verification methods until now. In this paper we give a formal proof that logic verification using *BMDs is polynomially bounded in both space and time when applied to the class of Wallace-tree like multipliers.

We introduce a two-staged Genetic Algorithm for optimizing weighted random pattern testing in a Built-in-Self-Test (BIST) environment. The first stage includes the OBDD-based optimization of input probabilities with regard to the expected test length. The optimization itself is constrained to discrete weight values which can directly be integrated in a BIST environment. During the second stage, the hardware-design of the actual BIST-structure is optimized. Experimental results are given to demonstrate the quality of our approach.

We present a tool to compute a synchronizing sequence for synchronous sequential circuits. It consists of three parts. One part is an OBDD-based approach combined with a heuristic algorithm for preventing a memory overflow. This approach potentially finds a minimum length reset sequence. The second part is an improved three-valued based greedy algorithm. Its synchronizing sequence is not minimal in all cases, but experiments show that it is actually very good. The third part of the tool (and the focus of this paper) is a routine to quickly decide the non-resetability of a design. In contrast to previous approaches this routine is based on sufficient functional conditions to prove the non-resetability of certain memory elements. For the first time results about the resetability of the largest ISCAS'89 benchmark circuits are presented.

Abstract| F ault simulation for synchronous sequential circuits is a very time-consuming task.The complexity of the task increases if there is no information about the initial state of the circuit.In this case an unknown initial state is assumed which is usually handled by i n troducing a three-valued logic.As it is well-known fault simulation based on this logic only determines a lower bound of the fault coverage.Recently it has been shown that fault simulation based on the multiple observation time test strategy can improve the accuracy of the fault coverage.In this paper we describe how this strategy can be successfully implemented based on Ordered Binary Decision Diagrams.Our experiments demonstrate the eciency of the fault simulation procedure developed.

Fault simulation for synchronous sequential circuits is a very time-consuming task. The complexity of the task increases if there is no information available about the initial state of the circuit. In this case, an unknown initial state is assumed which is usually handled by introducing a three-valued logic. It is known that fault simulation based upon this logic only determines a lower bound for the fault coverage achieved by a test sequence. Therefore, we developed a hybrid fault simulator H-FS combining the advantages of a fault simulator using the three-valued logic and of an exact symbolic fault simulator based upon binary decision diagrams. H-FS is able to handle even the largest benchmark circuits and thereby determines fault coverages much more accurately than previous algorithms using the three-valued logic.