Demo Data from VLDB 2026 / reviewers in the wild / expert
Lewis M. Terman
dblp:76/3518
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1966
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 67% Memory systems · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
digital circuit design |
0.0 | 1 | 1966 | An Investigation of the Potential of MOS Transistor Memories · IEEE Trans. Electron. Comput. 1966 |
Integrated circuit design
memory circuit design |
0.0 | 1 | 1966 | An Investigation of the Potential of MOS Transistor Memories · IEEE Trans. Electron. Comput. 1966 |
Memory systems
semiconductor memory |
0.0 | 1 | 1966 | An Investigation of the Potential of MOS Transistor Memories · IEEE Trans. Electron. Comput. 1966 |
Methods — techniques the papers use, named apart from their topics
performance characterization · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1966 | An Investigation of the Potential of MOS Transistor MemoriesabstractThe design and performance characteristics of a 128X64 MOS transistor memory is given. The storage cell used operates with a low standby power, 0.1 mW. The memory operates with a 12-ns access time, 35-ns read cycle time, and a 60-ns write cycle time. Peter Pleshko, Lewis M. Terman |
IEEE Trans. Electron. Comput. | 2 |