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Gregory L. Ries

dblp:76/3867 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1999
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware reliability and fault tolerance · 56% Electronic design automation · 28% Performance modeling and evaluation · 16%
Computer networks
1 paper
Internet architecture and protocols · 100%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance
fault injection
0.021999
Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation · IEEE Trans. Software Eng. 1999
Dependability Analysis of a High-Speed Network Using Software-Implemented Fault Injection and Simulated Fault Injection · IEEE Trans. Computers 1998
Electronic design automation › hardware verification and test
fault modeling
0.011999
Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation · IEEE Trans. Software Eng. 1999
Electronic design automation › hardware verification and test › fault simulation
hierarchical fault simulation
0.011999
Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation · IEEE Trans. Software Eng. 1999
Hardware reliability and fault tolerance
soft errors
0.011999
Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation · IEEE Trans. Software Eng. 1999
Performance modeling and evaluation › simulation › simulation-based evaluation
fault injection simulation
0.011998
Dependability Analysis of a High-Speed Network Using Software-Implemented Fault Injection and Simulated Fault Injection · IEEE Trans. Computers 1998
Hardware reliability and fault tolerance › fault injection
software fault injection
0.011998
Dependability Analysis of a High-Speed Network Using Software-Implemented Fault Injection and Simulated Fault Injection · IEEE Trans. Computers 1998
Hardware reliability and fault tolerance
dependability analysis
0.011999
Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation · IEEE Trans. Software Eng. 1999
Performance modeling and evaluation
simulation
0.011999
Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation · IEEE Trans. Software Eng. 1999
Internet architecture and protocols
local area network
0.011998
Dependability Analysis of a High-Speed Network Using Software-Implemented Fault Injection and Simulated Fault Injection · IEEE Trans. Computers 1998

Methods — techniques the papers use, named apart from their topics

transistor-level simulation · 0.0fault injection · 0.0
YearPublicationVenuePosition
1999 Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation
abstract
This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. In this methodology, effects of low-level (i.e., transistor or circuit level) faults are propagated to higher levels (i.e., system level) using fault dictionaries. The primary fault models are obtained via simulation of the transistor-level effect of a radiation particle penetrating a device. The resulting current bursts constitute the first-level fault dictionary and are used in the circuit-level simulation to determine the impact on circuit latches and flip-flops. The latched outputs constitute the next level fault dictionary in the hierarchy and are applied in conducting fault injection simulation at the chip-level under selected workloads or application programs. Faults injected at the chip-level result in memory corruptions, which are used to form the next level fault dictionary for the system-level simulation of an application running on simulated hardware. When an application terminates, either normally or abnormally, the overall fault impact on the software behavior is quantified and analyzed. The system in this sense can be a single workstation or a network. The simulation method is demonstrated and validated in the case study of Myrinet (a commercial, high-speed network) based network system.
Zbigniew T. Kalbarczyk, Ravishankar K. Iyer, Gregory L. Ries, Jaqdish U. Patel, Myeong S. Lee, Yuxiao Xiao
IEEE Trans. Software Eng.3
1998 Dependability Analysis of a High-Speed Network Using Software-Implemented Fault Injection and Simulated Fault Injection
abstract
This paper presents a dependability study of high-speed, switched Local Area Networks (LANs) using Myrinet as an example testbed (with theoretical speeds of 2.56 Gbps). The study uses results of two fault injection methods, simulated fault injection and software-implemented fault injection (SWIFI), to analyze the application-level impact of transient faults injected into the network interface hardware. These results include a number of errors, such as dropped or corrupt messages, host interface or host resets, and local or remote host interface hangs. The paper presents the study in two parts: First, the results from the SWIFI method in the real system are used as a basis to validate the simulation and identify the major factors leading to differences between the methods. A comparison between the two injection methods shows that they agree for 83 percent of the fault injections. The results, however, vary greatly, depending on the fault type considered. The study also presents an analysis of the effects of varying workload intensity, host platform, and interface function targeted by the injection. An example of this analysis is to show that the function targeted has a significant impact on the fault activation rate. Finally, the study identifies two mechanisms by which faults may propagate from the interface to other parts of the network; in one example, this propagation caused the interface's host computer to reboot, while another caused a remote interface in the network to hang.
David T. Stott, Gregory L. Ries, Mei-Chen Hsueh, Ravishankar K. Iyer
IEEE Trans. Computers2