Battery-less embedded systems powered by energy harvesting eliminate the need for battery maintenance and enable their deployment in remote environments. However, their intermittent execution, disrupted by unpredictable power failures, complicates data processing. Solutions for intermittency management gravitate around one key technique: checkpointing volatile data before power failures, and retrieving data at system reboot. Moreover, since data transmission is a major source of energy consumption, performing computations directly ondevice is essential. Initially used for simple tasks such as goods identifications, battery-less systems are now being applied to more energy-intensive tasks such as image recognition leveraging machine learning algorithms such as Convolutional Neural Networks (CNNs). In this paper, we introduce Circadia, a checkpointing strategy dedicated to CNN inference in battery-less systems. By leveraging the structured dataflow and control flow of CNNs, Circadia strategically places checkpoints within the CNN code to ensure task termination, data consistency, and low energy consumption. By design, Circadia has a linear complexity relative to model size, a significant improvement over the closest state-of-the-art checkpointing method, which has cubic complexity. This enables Circadia to handle much larger CNNs. Experimental results, on both generated and state-of-the-art embedded CNNs, show that its checkpoint placement time is several orders of magnitude lower than existing approaches, while its energy consumption at runtime remains nearly identical.

The control of real-time systems often requires taking into account simultaneous access in true parallelism to shared resources. This is particularly the case for multicore execution platforms. Timed automata or time Petri nets do not capture these features directly. We first define High-level Colored Time Petri Net (HCTPN) that extends time Petri Nets with color and high-level functionality encompassing both timed multi-enableness of transitions and sequential pseudo code. We then extend HCTPN with stopwatches to allow the modeling of preemptive scheduling, which is an important feature in the real-time context. We prove that the reachability problem is decidable for HCTPN but is undecidable for HCTPN with stopwatches, and we propose an abstraction of the state space for these models. We apply this approach to model a preemptive multi-core real-time application that uses a spinlock mechanism in order to check all possible execution paths, interleaving of service calls, and preemptive scheduling.

We evaluate HARVEST (Hardware Accelerated Runtime Verification for Embedded SofTware), a runtime error detection mechanism for embedded software running on standard SoPC architectures,i.e., one (or more) processor(s) and an FPGA on a single chip. The program under monitoring runs on the processor(s), while a trace analysis module running on the FPGA detects errors in its execution. The hardware implementation of trace analysis minimizes the performanceimpact and achieves a very low error reporting latency (a few processor cycles). In this article, we evaluate the suitability of using HARVEST to detect errors resulting from transient physical faults. We explain how HARVEST is used to monitor a complex software component (Trampoline RTOS) on a commercially available hardware platform (Microchip SmartFusion2). We measure the overhead of the resulting instrumentation on system resources. We then evaluate its performance in detecting silent data corruptions, based on a systematic simulation of bit flips at the instruction set architecture level. We report a detection rate of up to 90.2% for a fairly low system resource overhead, suggesting an interesting trade-off for designers of highly constrained critical systems.

Battery-free devices enable sensing in hard-to-access locations, opening up new opportunities in various fields such as healthcare, space, or civil engineering. Such devices harvest ambient energy and store it in a capacitor. Due to the unpredictable nature of the harvested energy, a power failure can occur at any time, resulting in a loss of all non-persistent information (e.g., processor registers, data stored in volatile memory). Checkpointing volatile data in non-volatile memory allows the system to recover after a power failure, but raises two issues: (i) spatial and temporal placement of checkpoints; (ii) memory allocation of variables between volatile and non-volatile memory, with the overall objective of using energy as efficiently as possible. While many techniques rely on the developer to address these issues, we present Schematic,a compiler technique that automates checkpoint placement and memory allocation to minimize the overall energy consumption. Schematicensures that programs will eventually terminate (forward progress property). Moreover, checkpoint placement and memory allocation adapt to the size of the energy buffer and the capacity of volatile memory. Schematictakes advantage of volatile memory (VM) to reduce the energy consumed, by automatically placing the most used variables in VM. We tested Schematicfor different experimental settings (size of volatile memory and capacitor) and results show an average energy reduction of 51 % compared to related techniques.

By relying on ambient energy, battery-less devices significantly increase the autonomy of IoT devices, enabling maintenance-free operation in remote locations. However, due to the scarcity of ambient energy, these devices rely on capacitors to buffer energy, and alternate between power-off phases where the device is harvesting energy and computation bursts. In most existing techniques, the device resumes execution only when the capacitor is full. However, we argue that doing so is sub-optimal. Instead, we advocate that waking-up the device sooner may yield better performance since the microcontroller consumes less power when operating at lower voltage. To this extent, we introduce EarlyBird, a technique that automatically computes a fine-tuned wake-up voltage for each resume point. EarlyBird leverages static analysis to determine how much energy is needed before resuming from a given program location, and provides a runtime library to enforce the early wake-up strategy. We evaluated how EarlyBird improves existing checkpointing techniques and results show an increase in the number of benchmarks executed per minute of up to 5.65×.

The SecureV (also known as SecV) project offers an innovative, open-source hardware, secure, and high-performance processor core based on the RISC-V ISA. The originality of the approach lies in the integration of a complete solution to increase security based on dynamic code transformation, covering 4 of the 5 NIST11National Institute of Standards and Technology functions of cybersecurity via monitoring (identify, detect), obfuscation (protect), and dynamic adaptation (react).

The control of real-time systems often requires taking into account simultaneous access in true parallelism to shared resources. This is particularly the case for multi-core execution platforms. Timed automata or time Petri nets do not capture these features directly. We propose extending time Petri Nets with color and high-level functionality encompassing both timed multi-enableness of transitions and sequential pseudo code. We prove that the reachability problem is decidable for this model on which an on-the-fly TCTL model checking algorithm is efficiently implemented in the tool ROMEO. We apply this approach to modeling a multi-core real time spinlock mechanism in order to check all possible execution paths and interleaving of service calls.

The conformance of a real time operating system (RTOS) to the OSEK/VDX standard is usually achieved by doing tests where a set of test cases is performed on the RTOS. However, in an embedded system, it is often necessary to specialize (configure) the code of the RTOS according to the requirements of the application. For such specialized RTOS, some conformance test cases can not be applied because they need some functionalities that are not supported anymore. This paper presents a model-based conformance verification of a RTOS with the OSEK/VDX standard. The method is applied on Trampoline RTOS which is used both for industry and academic purposes and which have been entirely and formally modeled by a product of extended finite automata embedding its source code. The first step is the construction of a complete model that describes the interaction between the application and the RTOS. In the second step all OSEK/VDX conformance test cases are translated into observers and composed with the complete model. Then, for a particular application, The observers allow to check if the RTOS model meets the OSEK/VDX specification. The interest of our approach is twofold: i) it allows to check the OSEK/VDX conformance of the complete version of the Trampoline RTOS; ii) for a specialized version of the RTOS, it identifies the relevant test cases for the given application, that require a very carefully conformance testing.

In an embedded system, the specialization of the code of the real-time operating system (RTOS) according to the requirements of the application allows one to remove unused services and other sources of dead code from the binary program. The typical specialization process is based on a mix of precompiler macros and build scripts, both of which are known for being sources of errors. In this article, we present a new model-based approach to the design of application-specific RTOS. Starting with finite state models describing the RTOS and the application requirements, the set of blocks in the RTOS code actually used by the application is automatically computed. This set is used to build an application-specific RTOS model. This model is fed into a code generator to produce the source code of an application-specific RTOS. It is also used to carry on model-based validations and verifications, including the formal verification that the specialization process did not introduce unwanted behaviors or suppress expected ones. To demonstrate the feasibility of this approach, it is applied to specialize Trampoline, an open-source implementation of the AUTOSAR OS standard, to an industrial case study from the automotive domain.

This article introduces STM-HRT, a nonblocking wait-free software transactional memory (STM) for hard real-time (HRT) multicore embedded systems. Resource access control in HRT systems is usually implemented with lock-based synchronization. However, these mechanisms may lead to deadlocks or starvations and do not scale well with the number of cores. Most existing nonblocking STM are not suitable for HRT systems, because it is not possible to find an upper bound of the execution time for each task. In this article, we show how STM-HRT can be a robust solution for resource sharing in HRT multicore systems. We provide a detailed description of STM-HRT architecture. We propose a set of arguments to establish the functional correctness of its concurrency control protocol. Finally, as part of a real-time analysis, we derive upper bounds on the computations required to access shared data under STM-HRT.

Currently the development of embedded software managing hardware devices that fulfills industrial constraints (safety, real time constraints) is a very complex task. To allow an increased reusability between projects, generic device drivers have been developed in order to be used in a wide range of applications. Usually the level of gener-icity of such drivers require a lot of configuration code, which is often generated. However, a generic driver requires a lot of configuration and need more computing power and more memory needs than a specific driver. This paper presents a more efficient methodology to solve this issue based on a formal modeling of the device and the application. Starting from this modeling, we use well-known game theory techniques to solve the driver model synthesis problem. The resulting model is then translated into the actual driver embedded code with respect to an implementation model. By isolating the model of the device, we allow more reusability and interoperability between devices for a given application, while generating an application-specific driver.

This paper introduces an OSEK/VDX operating system implementation. OSEK/VDX is an industry standard for real-time operating system used in the field of automotive embedded software. This implementation is proposed in the context of the open source software, which interest needs not to be demonstrated any more. The paper explains the main implementation choices as well as the technique proposed for the generation of a real-time application. This implementation is nowadays available for three targets: Infineon C167, Darwin/PowerPC and Linux/x86.

The quality of a real-time high-end virtual reality system depends on its ability to draw millions of textured triangles in 1/60 s. The idea of using commodity PC 3D accelerators to build a parallel machine instead of custom ASICs seems more and more attractive as such chips are getting faster. If image parallelism is used, designers have the choice between two distributions: line interleaving and square block interleaving. Having a fixed block shape and size makes chip design easier. A PC 3D accelerator has a cost-effective external bus and an on-chip texture cache. The performance of such a cache depends on spatial locality. If the image is rendered on multiple engines, this locality is reduced. Locality and load balancing depend on the distribution scheme of the machine. This paper investigates the impact of the distribution scheme on the performance of such a machine. We use detailed cache and memory system simulations with virtual reality benchmarks running on different configurations. We show that: (i) both distributions have the same maximum performance with less than 16 processors, but the square block has a better speedup with 64 processors; (ii) the best SLI (scan-line interleaving) block size depends on the number of processors of the machine and is not suitable for a scalable chip with a fixed block size; and (iii) using a large triangle buffer in the texture mapping engine has a very important impact on the performance.

As technology enables to integrate real-time good quality 30 rendering in a single chip, the classicalproblem of the gap between internal data bandwidth and external memories arisea.The texture mapping function requires a twmendous number of texture accesses and many past implementations have been based on costly high bandwidth external memory.OUT impact study of texture cache used with today's commercial representative 30 software shows that it is possible to render 100 million pixels per second while using an internal cache smaller than 32 KB and a PC memory bus for textures.Texture blocking and number of requests on the cache contribute mainly to those Tesults.Building a high performance parallel subsystem based on such a chip may become an interesting opportunityfor 1eadingpeTformance3D graphic manufacturers though many problems have been observed with caches in parallel machines.As far as texture accesses are concerned, we show that image parallelism generates poor performance with caches.But triangle parallelism scales with multiple rendering processors, each having its own texture cache and the speedup is nearly linear.'A texrl is a pixel in the texture map

Mismatches between on-chip high performance CPU and data access times is the basic reason for the increasing gap between peak and sustained performance in distributed memory parallel computers. We propose the concept of balanced architectures, based on a network with a dynamic topology and communication patterns determined at compile time. The corresponding processing element is a cacheless CPU, which can achieve a 1 FLOP/clock cycle rate. Network and PE features are presented. An example shows that balanced architectures keep efficiency when scaling.

The authors present RAPID a highly parallel processor which includes an extended relational algebra and text retrieval capacities in its instruction set. RAPID operates in parallel with the transfer of relevant data on the host machine bus, in a null apparent time. It is implemented with several copies of a specialized component using RISC (reduced-instruction-set-computer)-like technology, though its instructions are very high-level ones. It fully uses the resources of HCMOS3 technology and of full-custom design. A first version of the processor is presently being implemented.>