Dynamic voltage scaling (DVS) is an effective method for reducing processor power consumption. We present a compiler-based technique for DVS-based power optimizations of multimedia applications in the context of the Multi-Level Computing Architecture (MLCA) a novel architecture for parallel systems-on-a-chip. Our technique combines dependence analysis of long-running loops with profiling information in order to identify the slack available in the execution of parallel tasks. DVS is then applied to slow down processors executing noncritical-path tasks, reducing power with little or no impact on execution time. We evaluate our technique using realistic multimedia applications and a simulator of the MLCA. The results demonstrate that up to 10% savings in processor power consumption can be achieved with no more than 1.5% increase in execution time. Although our technique is developed in the context of MLCA, we believe that it is applicable in the broader context of task-level parallelism in multimedia applications.

As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is required, including high-level cache simulation. We propose to perform this cache simulation by defining a metric to represent memory behavior independently of cache structure and back-annotate this into the original application. While the annotation phase is complex, requiring time comparable to normal address trace based simulation, it need only be performed once per application set and thus enables simulation to be sped up by a factor of 20 to 50 over trace based simulation. This is important for embedded systems, as software is often evaluated against many input sets and many architectures. Our results show the technique is accurate to within 20% of miss rate for uniprocessors and was able to reduce the die area of a multiprocessor chip by a projected 14% over a naive design by accurately sizing caches for each processor.

Rapid growth in the internet and enterprise network traffic, need by both subscribers and operators to provide for differentiated services, and the constant evolution of wireline and wireless networking functions, algorithms and standards, is leading to a high demand for ultra high speed, yet programmable, network processors and ASICs. This session will introduce the design of network processors, and highlight important validation and test challenges associated with network processors and ASICs. The first speaker in this session will review the architecture of a typical OC-192 network processor – a highly complex system-on-chip, consisting of multiple processors, specialized hardware blocks, multiple high-speed embedded memory units, and a highly concurrent and complex on-chip interconnect structure. The talk will analyze the validation and manufacturing test problems of hardware-software GHz network processor chips, which have to use aggressive architecture designs and nano-meter technologies to obtain the required multi-GHz speed, while relying on the presence of multiple processors to provide the necessary flexibility. The second talk will address testing of embedded GHz network processors. In particular, it will describe the challenges faced in testing a specific high-speed low-power network processor chip, which includes two custom-design 64-bit MIPS processors, 0.5MB of L2 cache, and multiple high speed communication blocks, such as gigabit-ethernet, hypertransport, and double-data-rate memory controllers. Some test solutions will be presented, and major test challenges that need to be addressed will be listed. The third talk in this session will address the problem of delay testing in communications chips. In communication devices such as network switches and routers, there usually are multiple unrelated clocks controlling various interfaces and logic. These multiple clock domains presents unique challenges in production testing since it becomes very difficult to predict when the expected output will show up at the pin boundary. The talk will show why delay defects need to be addressed, and how to deal with cycle uncertainty problem during production testing. It will present a novel compaction technique used to deal with the test data volume explosion resulting from including of delay defect screening tests. Proceedings of the 20 th IEEE VLSI Test Symposium (VTS’02) 1093-0167/02 $17.00 © 2002 IEEE

The need for network processors capable of forwarding IP packets at OC-192 and higher data rates has been well established. At the same time, there is a growing need for complex tasks, like packet classification and differentiated services, to be performed by network processors. At OC-768 data rate, a network processor has 9 nanoseconds to process a minimum-size IP packet. Such ultra high-speed processing, involving complex memory-intensive tasks, can only be achieved by multi-CPU distributed memory systems, using very high performance on-chip communication architectures. In this paper, we propose a novel communication network architecture for 8-CPU distributed-memory systems that has the potential to deliver the throughput required in next generation routers. We then show that our communication architecture can easily scale to accommodate much greater number of network nodes. Our network architecture yields higher performance than the traditional bus and crossbar yet has low implementation cost. It is quite flexible and can be implemented in either packet or circuit switched mode. We will compare and contrast our proposed architecture with busses and crossbars using metrics such as throughput and physical layout cost.

With the projected explosion of low-cost bandwidth availability, the intensive processing tasks and service hosting will move close to consumers on the "intelligent edge" of the network, where a significant portion of the future storage, processing and network management will take place. We address the rationale for this change, the characteristics of the network processor architecture required to address it, and the software development tools needed in order to improve time-to-market without sacrificing embedded software performance.