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Donald R. Schertz

dblp:76/4493 · DBLP profile ↗
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4ranked-venue papers
3as first author
0since 2021 · last 1975
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Electronic design automation · 96% Distributed systems · 4%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test
0.031975
Comments on "Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences" · IEEE Trans. Computers 1975
A New Representation for Faults in Combinational Digital Circuits · IEEE Trans. Computers 1972
On the Design of Multiple Fault Diagnosable Networks · IEEE Trans. Computers 1971
Electronic design automation › hardware verification and test
test generation
0.021975
Comments on "Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences" · IEEE Trans. Computers 1975
A New Representation for Faults in Combinational Digital Circuits · IEEE Trans. Computers 1972
Electronic design automation › hardware verification and test › test generation
boolean difference
0.011975
Comments on "Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences" · IEEE Trans. Computers 1975
Electronic design automation › hardware verification and test
fault detection
0.011975
Comments on "Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences" · IEEE Trans. Computers 1975
Electronic design automation › hardware verification and test › test generation
minimal test set
0.011975
Comments on "Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences" · IEEE Trans. Computers 1975
Electronic design automation › hardware verification and test › fault diagnosis
multiple fault diagnosis
0.011971
On the Design of Multiple Fault Diagnosable Networks · IEEE Trans. Computers 1971
Distributed systems
fault tolerance
0.011974
Fault-Tolerant Computing: An Introduction · IEEE Trans. Computers 1974
Electronic design automation › logic synthesis
combinational logic synthesis
0.011971
On the Design of Multiple Fault Diagnosable Networks · IEEE Trans. Computers 1971

Methods — techniques the papers use, named apart from their topics

path sensitization · 0.0connection graph analysis · 0.0boolean equation manipulation · 0.0boolean difference · 0.0
YearPublicationVenuePosition
1975 Comments on "Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences"
abstract
In the above paper1, the partial Boolean difference is defined and an algorithm for deriving complete minimal test input sequences for single-fault detection is given. In this correspondence, it is shown that the presentation of the algorithm is inadequate with respect to the need for multiple path sensitization. It is further shown that the computational procedure used in footnote 1 does not guarantee minimality of the test set and does not permit the extension to fault location as claimed in the paper.
Gernot Metze, Donald R. Schertz, Kilin To, Gordon Whitney, Charles R. Kime, Jeffrey D. Russell
IEEE Trans. Computers2
1974 Fault-Tolerant Computing: An Introduction
abstract
FAULT-TOLERANT computing has been defined as "the ability to execute specified algorithms correctly regardless of hardware failures, total system flows, or program fallacies" [1]. This definition of fault-tolerant computing leads directly to three major subdivisions [2]:
Donald R. Schertz
IEEE Trans. Computers1
1972 A New Representation for Faults in Combinational Digital Circuits
abstract
A new representation for faults in combinational digital circuits is presented. Faults that are inherently indistinguishable are identified and combined into classes that form a geometric structure that effectively subdivides the original circuit into fan-out-free segments. This fan-out-free characteristic allows a simplified analysis of multiple fault conditions. For certain circuits, including all two-level single-output circuits, it is shown that the detection of all single faults implies the detection of all multiple faults. The behavior of any circuit under fault conditions is represented in terms of the classes of indistinguishable faults. This results in a description of the faulty circuit by means of Boolean equations that are readily manipulated for the purpose of fault simulation or test generation. A connection graph interpretation of this fault representation is discussed. Heuristic methods for the selection of efficient tests without extensive computation are derived from these connection graphs.
Donald R. Schertz, Gernot Metze
IEEE Trans. Computers1
1971 On the Design of Multiple Fault Diagnosable Networks
abstract
This paper considers the design of diagnosable combinational networks. The diagnosability criterion used here requires that the single fault detection test set for the network also detects all multiple faults. Several recent studies in the area of multiple fault diagnosis are reviewed and the results which are pertinent to this investigation are summarized. It is shown that, under certain conditions, internal fan-out may be present without adversely affecting the detection of multiple faults. These results suggest design techniques which lead to readily diagnosable networks.
Donald R. Schertz, Gernot Metze
IEEE Trans. Computers1