Demo Data from VLDB 2026 / reviewers in the wild / expert
Min-Wen Du
dblp:76/4588
· DBLP profile ↗
5ranked-venue papers
4as first author
0since 2021 · last 1986
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 4 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 100% | |
| Theoretical computer science
2 papers |
Mathematical optimization · 52% Computational complexity · 26% Automata and formal languages · 22% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › test generation › fault test generation
fault detection test generation |
0.0 | 3 | 1986 | Multiple Stuck-Fault Detection and Location in Multivalued Linear Circuits · IEEE Trans. Computers 1986 Circuit Structure and Switching Function Verification · IEEE Trans. Computers 1973 Multiple Fault Detection in Combinational Circuits: Algorithms and Computational Results · IEEE Trans. Computers 1973 |
Electronic design automation
hardware verification and test |
0.0 | 3 | 1986 | Multiple Stuck-Fault Detection and Location in Multivalued Linear Circuits · IEEE Trans. Computers 1986 Circuit Structure and Switching Function Verification · IEEE Trans. Computers 1973 Multiple Fault Detection in Combinational Circuits: Algorithms and Computational Results · IEEE Trans. Computers 1973 |
Electronic design automation › hardware verification and test › fault detection
multiple fault detection |
0.0 | 2 | 1973 | Circuit Structure and Switching Function Verification · IEEE Trans. Computers 1973 Multiple Fault Detection in Combinational Circuits: Algorithms and Computational Results · IEEE Trans. Computers 1973 |
Electronic design automation › hardware verification and test › functional verification
logic verification |
0.0 | 1 | 1973 | Circuit Structure and Switching Function Verification · IEEE Trans. Computers 1973 |
Mathematical optimization › combinatorial optimization
covering problems |
0.0 | 1 | 1972 | A Way to Find a Lower Bound for the Minimal Solution of the Covering Problem · IEEE Trans. Computers 1972 |
Mathematical optimization
discrete optimization |
0.0 | 1 | 1972 | A Way to Find a Lower Bound for the Minimal Solution of the Covering Problem · IEEE Trans. Computers 1972 |
Computational complexity
lower bounds |
0.0 | 1 | 1972 | A Way to Find a Lower Bound for the Minimal Solution of the Covering Problem · IEEE Trans. Computers 1972 |
Automata and formal languages › finite automata › sequential machines
sequential circuits |
0.0 | 1 | 1971 | Comments on "Nonlinear Sequential Circuits" · IEEE Trans. Computers 1971 |
Methods — techniques the papers use, named apart from their topics
bin packing · 0.0expansion · 0.0decomposition theory · 0.00-1 covering problem · 0.0polynomial representation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1986 | Multiple Stuck-Fault Detection and Location in Multivalued Linear CircuitsabstractIn this correspondence, we present procedures for constructing universal fault detection test sets as well as fault location test sets for multivalued linear circuits, under a multiple stuck-fault model. The bin packing problem is involved in the procedures. The sizes of the fault detection test set and the fault location test set constructed for an n- variable v-valued linear tree circuit are 1 + ⌈n/(v − 1)⌉ and 1 + ⌈n/ ⌊log2 v⌋ ⌉, respectively. It has been proved that the sizes listed above are optimal for some cases. Chuen-Liang Chen, Min-Wen Du |
IEEE Trans. Computers | 2 |
| 1973 | Multiple Fault Detection in Combinational Circuits: Algorithms and Computational ResultsabstractA new approach is developed for finding multiple fault detection tests under quite arbitrary fault models. Computational results are reported and discussed. Min-Wen Du, C. Dennis Weiss |
IEEE Trans. Computers | 1 |
| 1973 | Circuit Structure and Switching Function VerificationabstractA new approach is presented for the design of multiple fault detection tests in which the structure of a combinational circuit is used to reduce the number of input combinations required. The structure is defined by the interconnection of the basic elements, each of arbitrary complexity. The fault model assumes that the functions realized by the basic elements may undergo any deviation whatsoever, but that the circuit structure is fault free. Thus, arbitrary combinations of multiple faults within one or more basic elements are included in the model. Decomposition theory can be used to verify that a set of input combinations is a multiple fault detection test set under this model. A process called expansion will be introduced to simplify this task. A well-defined procedure is given for deriving a suitable test set which for some circuits is minimal or near minimal. It will yield a multiple fault detection test of length less than 2nfor any circuit with a nontrivial nondisjoint decomposition, defined by a basic-element partition. Higher order basic-element partitions are introduced as a generalization. An upper bound is given on the length of a multiple fault detection test for any circuit with a given structure, independent of the function realized on the structure. The bound is tighter when function information is also used. Min-Wen Du, C. Dennis Weiss |
IEEE Trans. Computers | 1 |
| 1972 | A Way to Find a Lower Bound for the Minimal Solution of the Covering ProblemabstractThis correspondence derives a lower bound for the size of a minimal solution of a 0-1 covering problem. Min-Wen Du |
IEEE Trans. Computers | 1 |
| 1971 | Comments on "Nonlinear Sequential Circuits"abstractThis correspondence describes a way to find the co-efficients of the polynomials which were used to represent nonlinear sequential circuits.1 Min-Wen Du |
IEEE Trans. Computers | 1 |