Abstract Computer-aided diagnosis (CADx) systems often involve error-prone and/or manual processes. Recent studies show that various machine learning models have the potential to improve the accuracy of CADx systems. However, existing models suffer from low prediction accuracy. In this work, we present research findings to improve the effectiveness of CADx systems for detecting skin diseases by adopting optimized ensemble machine learning models. The investigation encompasses the exploration of three popular classification methods: linear discriminant analysis (LDA), support vector machine (SVM), and convolutional neural network (CNN); two customized CNN models: LeNet-5 and ResNet; and an ensemble model of CNN with SVM. The ensemble CNN-SVM model is optimized using techniques such as feature aggregation and weight adjustments. Skin lesion images from Kaggle’s Human Against Machine 10000 (HAM10000) are used to train and test all classification models. Through rigorous experiments, the results highlight the compelling efficacy of the ensemble CNN-SVM model, unveiling heightened accuracy of up to 92% (from ResNet accuracy of 88%, CNN accuracy of 85%, SVM accuracy of 83%, LeNet-5 accuracy of 77%, and LDA accuracy of 75%). The models are tested on another dataset from Kaggle’s Melanoma Skin Cancer Dataset of 10000 Images; new results follow a similar trend to those using the HAM10000 dataset. The outcome of this work has profound implications for artificial intelligence (AI) accelerated engineering applications in advancing the effectiveness of skin disease treatment through diagnosis systems.

Protein-protein interaction (PPI) is an important field in bioinformatics which helps in understanding diseases and devising therapy. PPI aims at estimating the similarity of protein sequences and their common regions. STRIKE was introduced as a PPI algorithm which was able to achieve reasonable improvement over existing PPI prediction methods. Although it consumes a lower execution time than most of other state-of the-art PPI prediction methods, its compute-intensive nature and the large volume of protein sequences in protein databases necessitate further time acceleration. In this paper, we develop hardware accelerator designs for the STRIKE algorithm. Results indicate that the weighted STRIKE accelerator execution times are about 10x longer than the unweighted STRIKE accelerator execution times. To further accelerate the performance of the weighted STRIKE, a parallel module accelerator organization duplicating the weighted STRIKE modules is introduced, achieving near linear speedups for long sequences of 100 or more characters. As demonstrated by Verilog simulations and FPGA runs, the weighted STRIKE module accelerator exhibits three orders of magnitude speed improvement over multi-core and cluster computers. Much higher speedups are possible with the parallel module accelerator.

In this work, we introduce a software-defined unmanned aerial systems (UAS) model, which can provide access to sensitive places where Wi-Fi communication is most needed for rescue operations. The proposed UAS model is equipped with smart obstacle avoiding assistance and can navigate in a global positioning system (GPS) denied environments to accomplish rescue operations successfully. We conduct indoor simulations of the developed UAS model with mounted light detection and ranging (LIDAR) sensors. Although the experimental results suggest that a larger battery weight and a higher energy consumption are needed than theoretically estimated, the proposed UAS model shows promise to be used in smart disaster management.

This paper introduces the Spidergon-Donut (SD) on-chip interconnection network for interconnecting 1,000 cores in future MPSoCs and CMPs. Unlike the Spidergon network, the SD network which extends the Spidergon network into the second dimension, significantly reduces the network diameter, well below the popular 2D Mesh and Torus networks for one extra node degree and roughly 25 percent more links. A detailed construction of the SD network and a method to reshuffle the SD network's nodes for layout onto the 2D plane, and simple one-to-one and broadcast routing algorithms for the SD network are presented. The various configurations of the SD network are analyzed and compared including detailed area and delay studies. To interconnect a thousand cores, the paper concludes that a hybrid version of the SD network with smaller SD instances interconnected by a crossbar is a feasible low-diameter network topology for interconnecting the cores of a thousand core system.

Conotoxin classification could assist in the study of the structure function relationship of ion-channels and receptors as well as identifying potential therapeutics in the treatment of a wide variety of diseases such as schizophrenia, chronic pain, cardiovascular and bladder dysfunction. In this study, we introduce a novel method (Toxin-AAM) for conotoxin superfamily classification. Toxin-AAM incorporates evolutionary information using a powerful means of pairwise sequence comparison and amino acid composition knowledge. The combination of the sequential model and the discrete model has made the Toxin-AAM method exceptional in classifying conotoxin superfamily, when compared to other state-of-the-art techniques.

Abstract Two image processing applications, edge detection and image resizing, are studied in this paper on two HPC platforms namely the Cell BE and the Blue Gene/L machines. In this paper we focus on the performance scalability of the studied applications. Our results show that the scale of the problem to be solved highly affects the fitness of the platform. If the data set size is to fit into the Cell core, the fast on‐chip inter‐core communication of a multi‐core system pays back for its high technology design. On the other hand, the overhead of the distant communication in the massively parallel Blue Gene/L machine will only show its benefits for huge data set size that otherwise mandates multiple round‐trip data communications between the local memory of a core and main memory. Copyright © 2010 John Wiley & Sons, Ltd.

SUMMARY Multicore accelerators are used today to supplement traditional superscalar processors in massively parallel computer nodes with extra floating‐point computation power. This paper presents our parallelization and performance enhancement and evaluation of the conjugate gradient (CG) linear equation solver with enhanced matrix multiplication on the Cell Broadband Engine accelerator. The paper also compares the CG performance results on the Cell and two CG implementations on a computer with two quadcore Xeon processors, one with OpenMP and the other with OpenMPI. We also report the enhancements made on the CG code and performance analysis of CG on single and dual Cell Broadband Engine packages with 8 and 16 synergistic processing elements and on Xeon for heptadiagonal matrices, in particular to matrix multiplication and synchronization. We also report the communication and computation time breakdowns and the floating point operations per second ratio. Our parallel CG solver is shown to scale well with data size, grid dimensionality, and number of cores. Copyright © 2011 John Wiley & Sons, Ltd.

On-chip interconnection networks (OCINs) in many-core systems are key to the system's performance scalability. OCIN design constraints are governed by power, cost, latency, ease of routing, as well as others. As chips with 16 cores are around the corner, we focus on 16-core systems and consider 9 OCINs for 16-core MPSoCs. A key requirement of real time embedded systems is dependable timeliness. This directly translates into primarily, low diameter, and secondary, average distance requirements. As these are immediately linked to the network's topology in general, and the node degree and total link cost in particular, we also monitor the node degree and total link cost. For these 9 OCINs, we derive their diameters, average delays, node degrees, and total link costs. We compare these OCINs with respect to these network attributes in an attempt to identify the most suitable OCIN for 16-core MPSoC systems.

One major issue in the design of multi-core systems is scheduling execution threads on the many cores. Heterogeneity complicates the issue given the different types of cores with various functionality and power requirements. In a large multi-core chip with long interconnect latencies, minimizing thread migration costs is essential in minimizing the power consumption and maximizing performance. In this paper, we present a thread scheduling scheme for a class-based 2D Mesh-interconnected multi-core system which considers inter-core distances in its scheduling decisions. We also consider various thread migration policies in case a thread's previous core in unavailable and the thread must be reassigned to a different core. A performance simulator is developed to weigh the various thread scheduling and migration policies. The simulation results reveal that scheduling algorithms which both consider core affinity and support distance-based migration outperform the other considered algorithms.

It is critical for the network-on-chip in embedded multi-core and many-core chips to be scalable while limiting power consumption. With the router power dominating the network's power, one way to achieve this goal is by the design of on-chip interconnection networks with small diameters and simple routing. Herein, we present a few new unicast on-chip networks for interconnecting the cores with diameters superior to the popular 2D mesh.

Based on the recent design trend from giant chip-vendors, multicore systems are being deployed with multilevel caches to achieve higher levels of performance. Supporting real-time applications on multicore systems becomes a great challenge as caches are power hungry and caches make the execution time predictability worse. Studies show that timing predictability can be improved using cache locking techniques. However, level-1 (L1) entire locking may not be efficient if smaller amount of instructions/data compared to the cache size is locked. An alternative choice may be way locking. For some processors, way locking is possible at level-2 (L2) cache (not permitted at L1). Even though both L1 entire locking and L2 way locking improve predictability, it is difficult to justify the performance and power trade-off between these two locking mechanisms. In this work, we simulate a multicore system with two levels of caches to explore the impact of L1 entire locking and L2 way locking on the performance, power consumption, and predictability. Simulation results using FFT, DFT, and MPEG4 algorithms show that both performance and predictability can be increased and power consumption can be decreased by using a cache locking mechanism added to a cache memory hierarchy. Results also show that for FFT and DFT, L2 way locking outperforms L1 entire locking; but for MPEG4, L1 entire locking performs better than L2 way locking.

Massively deployed inside Sony PS3 platforms, the STI Cell Broadband Engine is a multi-core processor with a PowerPC host processor (PPE) and 8 synergic processor engines (SPEs). In this paper, we describe three image processing applications which we implemented on the Cell BE. We report the performance measured on one Cell blade with varying numbers of synergic processor engines enabled, and with varying application parameters. These results were compared to the results obtained on the Cell BE running a single PPE and with all 8 SPEs disabled. The results reveal the superior performance of image processing and SIMD-prone applications on the 9-core Cell BE processor over conventional RISC processors.

Oil reservoir simulation helps in extracting oil and in optimal well placement. This paper presents the parallelization, development, performance analysis, and profiling of a 2-phase oil-water reservoir simulator on a heterogeneous multi-core STI Cell computer. Despite the largely interdependent nature of the oil reservoir model equations, we obtained speedups of 6x with a 1D reservoir data. We boosted the performance by 2x with the right selection of compiler options. We also ran our application on the SystemSim simulator for collection of performance events. Profiling and trace analysis of the application were conducted through VAMPIR, a performance and trace analysis tool for HPC applications. The results from both tools are also presented.

This paper makes the case for the Hyper-Ring as the interconnect or NoC for many-cores. While other prominent candidates for many-core interconnect such as the torus and mesh have superior bisection bandwidth to the HR, their cost, number of links and chip area are much higher than the HR. The worst-case latency or maximum hop count is relatively inferior on the mesh, while that of the HR is comparative to that of the torus for about a 100 core nodes. Moreover, the HR resembles more the LANs and WANs which have dedicated gateway or router nodes. We present a many-core floorplan where adjacent pairs of cores share an L2 cache memory and where the cores are interconnected according the HR topology. We also address L2 cache partitioning and coherence in HR-connected many-core processors and how such a processor can be tolerant of faulty links and nodes. The HR-connected many-core processor is naturally tolerant of core and link faults owing to its double second directional rings. To keep the same amount of operational hardware and the same performance levels in the presence of faults, we present a circuit for bypassing faulty cores and replacing them by spare cores.

Presents an algorithm that solves the conflict resolution problem in fault-tolerant multicast-connected MINs. Without loss of generality, the authors apply the algorithm to reconfigure a four-path cube-based network. An intensive simulation study is conducted to reveal the performance improvement gained by the conflict resolution and fault-free path selection algorithm on the network under study. The simulation results indicate that the probability of failure to provide multicast connections using two paths is comparable to that of using three and four paths under various fault scenarios. The results also indicate that an effective reconfiguration algorithm based on two alternate paths has a great impact on the network performance in the presence of faults and conflicts.>

The complementary two-stage cube (C2SC) provides four paths between every source and destination pair so that all single faults and many multiple faults can be tolerated. One of the key issues in multiple-path multistage interconnection networks (MIN's) is the manner in which rerouting is achieved when the network has faults. In this paper, we present four reconfiguration schemes for broadcast connections of the C2SC in the presence of one or multiple faults, and these are: destination discriminator, divide and broadcast, decoded routing tag, and conservative schemes. A hardware implementation and a cost/performance analysis of the four schemes were carried out. The analysis includes comparison of hardware cost, reconfiguration time, cost-reconfiguration time product, and regularity and modularity. The cost/performance analysis and simulation results indicate that the destination discriminator scheme has the lowest cost-reconfiguration time product and has relatively high regularity and modularity.>

The problem of reconfiguration in a multicast-connected fault-tolerant multiple-path multistage interconnection networks (MIN) is discussed. The results of a simulation study conducted to evaluate the performance of the complementary two-stage cube (C2SC) network, a four-path cube-based network, under faults in the multicast mode are presented. The performance index used is the probability of failure to provide multicast connections due to faults and conflicts using two paths, three paths, and four paths out of all four possible paths. The results indicate that the probability of failure to provide multicast connection using two paths is comparable to that for using three and four paths. This implies that in order to reconfigure the C2SC MIN under faults, it is sufficient to consider only two paths.>