General Purpose Graphics Processing Units (GPGPUs) are extensively used in high-performance applications/systems, whose execution times may vary from a few days to months. Many times, these systems are expected to provide high reliability and availability. On the other hand, the high-throughput GPGPUs are fabricated with the latest cutting-edge technology. The shrinking transistor feature size and aggressive voltage scaling resulted in increased susceptibility to soft errors. Hence, GPGPU execution results cannot be trusted. This necessitates the employment of error detection and correction methods for reliable results. To mitigate soft error effects in the GPGPU execution pipeline, we propose a fault-tolerant microarchitecture called Triple modular Redundant Execution with idle Functional Units (TREFU) to detect and correct errors online. The proposed method is transparent to the application software. A new microarchitecture structure, replay buffer, is introduced to store temporary operands and results and used as a checkpoint. On error detection, the data in the duplicate copy of the replay buffers are used for Triple Modular Redundant (TMR) execution and error correction. The effectiveness of TREFU is demonstrated through the ISPASS 2009 and RODINIA benchmarks. TREFU's performance and power overheads are evaluated for an error-free run and at various error rates of executed instructions ranging from 1 to 50K. The simulation results show that complete error detection and correction across all threads can be achieved with a mean performance overhead of 4%, an average power overhead of 4%, and a peak power overhead of 5%.

In analog testing, usage of a single sinusoid as a test signal when compared to multitone signal, and fault detection with digital counting technique, facilitate the test implementation with simple built-in self-test hardware and make testing more cost effective. In this paper, a novel test-set-selection technique known as ExpoTan for testing linear-time-invariant (LTI) circuits is presented. The authors formulate the test generation problem with tan-1( ) and exponential functions for identification of a test signal with maximum fault coverage. For identification of a test signal the ExpoTan technique combines test generation and test-set-compaction tasks in a single phase and generates an efficient compacted test set. The experimental results show that the testing of LTI circuits using ExpoTan technique for the benchmark circuits achieves the required fault coverage with shorter testing time and test generation time

A new test-set selection technique based on the frequency-domain testing of analog circuits is presented in this paper. We propose a new automatic test pattern generation (ATPG) method known as MultiDetect for testing linear time invariant (LTI) circuits. The proposed technique is best suited for use of existing building blocks in systems-on-chip for implementation of an on-chip test-signal generator and test-response analyzer. The generated test set with the MultiDetect method can effectively detect and diagnose both soft and hard faults and does not require any precision analog signal sources or signal measurement circuits when implemented as built-in self-test (BIST). Testing of analog blocks based on circuit-transfer function makes our ATPG a general purpose method for all kinds of LTI circuits. A new novel test method causing the device under test to saturate or get out of saturation, to detect a fault with simple detection hardware, is also introduced in this paper. In our proposed novel test scheme, usage of a single sinusoid as a test signal when compared to multitone signal, and detection of faults with digital counting technique, facilitate the test implementation with simple BIST hardware and make testing more cost effective. The sinusoid is a very useful waveform for testing and analyzing LTI circuits. In the steady state, both the input and output of a stable LTI circuit are sinusoids of the same frequency. The relationship between the amplitudes and phase angles of the input and output sinusoids is frequency-dependent. Identification of a sinusoid that detects more faults results in an optimized test signal set. The technique used in the MultiDetect method for identification of a sinusoid results in an efficient compacted test set. The search for fault diagnosis is restricted to a limited set of faults, making diagnosis fast in the MultiDetect method. A methodology for test-set compaction of the MultiDetect technique is described and results of experiments on various test circuits are discussed. The proposed method is seen to be efficient for low-power applications. The experimental results show that the testing of LTI circuits using the MultiDetect technique for the benchmark circuits achieves the required fault coverage with much shorter testing time.