This paper discusses the design of two reconfiguration strategies for distributed memory multicomputer architectures under failures. The specific architectures to which we apply the techniques are hypercubes and meshes. The first scheme uses spare processors attached to certain processors in the hypercube or mash using a novel embedding technique. The second approach places spare processors along specific links in the hypercube or mesh. Both schemes involve the mapping of logical links of a virtual machine onto a set of physical links in the final reconfigured machine and hence suffer some performance degradation. We characterize the performance degradation through trace-driven simulation of real applications running on the faulty and reconfigured system. We find that the schemes have high reliability, suffer little degradation in performance, and are very low in cost.>

A wide variety of fault tolerance techniques for VLSI technology are examined. Device-, gate-, and function-levels fault models are described. The basic methods available to the designer of fault tolerance measures are introduced by surveying redundancy techniques. Techniques of fault detection that use space, time, and information redundancies, algorithm-based fault tolerance, in VLSI components, large-scale processor-level implementations of fault detection, fault tolerance in automated VLSI production systems are discussed. Reconfiguration of the system and recovery of system operation are described. Issues relating to the reconfiguration after discovery of a fault in fabrication or in operation are discussed. Recovery capabilities of a VLSI microprocessor are reviewed.>