Demo Data from VLDB 2026 / reviewers in the wild / expert
Slo-Li Chu
dblp:76/949
· DBLP profile ↗
17ranked-venue papers
13as first author
1since 2021 · last 2022
0000-0003-3999-7293ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 5 first-authorGraphics, computer vision, multimedia, augmented reality and games · 4 · 1 first-author · 1 since 2021Applied, interdisciplinary, general and emerging computing · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-authorDatabases, data management, data science and information retrieval · 1Theory of computation · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
GPUs and heterogeneous computing · 50% Energy-efficient computing · 50% | |
| Computer graphics and multimedia
1 paper |
Rendering · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing › GPU scheduling
GPU thread scheduling |
0.2 | 1 | 2014 | An Adaptive Thread Scheduling Mechanism With Low-Power Register File for Mobile GPUs · IEEE Trans. Multim. 2014 |
GPUs and heterogeneous computing › embedded GPU
mobile GPU |
0.2 | 1 | 2014 | An Adaptive Thread Scheduling Mechanism With Low-Power Register File for Mobile GPUs · IEEE Trans. Multim. 2014 |
Energy-efficient computing
power management |
0.2 | 1 | 2014 | An Adaptive Thread Scheduling Mechanism With Low-Power Register File for Mobile GPUs · IEEE Trans. Multim. 2014 |
Energy-efficient computing › memory energy efficiency
register file energy reduction |
0.2 | 1 | 2014 | An Adaptive Thread Scheduling Mechanism With Low-Power Register File for Mobile GPUs · IEEE Trans. Multim. 2014 |
Rendering
real-time rendering |
0.1 | 1 | 2014 | An Adaptive Thread Scheduling Mechanism With Low-Power Register File for Mobile GPUs · IEEE Trans. Multim. 2014 |
Methods — techniques the papers use, named apart from their topics
multiple power modes · 0.4adaptive thread scheduling · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | CFSM: a novel frame analyzing mechanism for real-time face recognition system on the embedded system
Slo-Li Chu, Chien-Fang Chen |
Multim. Tools Appl. | 1 |
| 2020 | CNN Based iPS Cell Formation Stage Classifier for Human iPS Cell Growth Status Prediction Using Time-lapse Microscopy ImagesabstractCNN classifiers using microscopy images to pick up induced pluripotent stem (iPS) cells from a lot of non-iPS cells ware proposed to improves efficiency of human iPS cell production. By selecting iPS-forming cells at early culture stage, it should be more promising to reduce a considerable amount of work. This paper proposes a CNN reprogramming stage classifier trained by respective types (grown into high-, medium, and low-growth status of iPS-like cells) of time-lapse images taken from the completed cell culturing process. These trained CNNs are used to classify a time-lapse image taken in cell culturing as one stage (a number of consecutive frames) of a respective set of trained time-lapse images. The differences between the actual stage with respective classified stages are than calculated to decide which stage of the completed cell this time-step image taken in cell culturing is near to, then to predict the iPS cell growth status that the culturing cells finally grow into. The method achieved the 85% accuracy to predict the growth status of culturing cells two days later, thus can be applicable for early selection suggestion of good iPS-forming cells. Slo-Li Chu, Li-Yu Lin, Ming-Dar Tsai, Kuniya Abe, Kazuhiro Sudo, Yukio Nakamura, Hideo Yokota |
BIBE | 1 |
| 2020 | Trend Training Based RNN for Human Induced Pluripotent Stem Cell Reprogramming Prediction Using Time-Lapse Microscopy ImagesabstractRecurrent Neural Network (RNN) operates on sequential data using a recurrent hidden state dependent on previous data. Even proved successful in many fields, RNNs suffer from vanishing and exploding gradient problems. Gating approach of LSTM and GRU solves these problems but lose prediction accuracies if short-term changes occur in time-lapse microscopy images taken in cell culture. This study uses trend training (feed forward and pre-training) based RNN to improve the prediction accuracy for human iPS cell reprogramming and formation in future culture. The feed forward RNN uses the prediction of each time-step in the next recursive batch training for the next prediction recursively to give recurrent RNN internal states approaching optimal. Pre-training gives optimal initial RNN parameters selected from RNN models pre-trained by sets of time-lapse images taken from a completed cell culture process. An example shows the predicted accuracies and iPS cell colony shapes by feed forward RNN are apparently better than those without the feed forward training, the accuracies and iPS cell colony shapes furthermore applying the pre-trained models are better than only using the feed forward training. Thirty experimental results show the proposed method achieved 0.752 (SD 0.137) accuracy in future 72 time-steps (1.5 days). Slo-Li Chu, Shao-Yu Sung, Ming-Dar Tsai, Kuniya Abe, Kazuhiro Sudo, Yukio Nakamura, Hideo Yokota |
BIBE | 1 |
| 2014 | Demand look-ahead memory access scheduling for 3D graphics processing units
Chih-Chieh Hsiao, Min-Jen Lo, Slo-Li Chu |
Multim. Tools Appl. | 3 |
| 2014 | An Adaptive Thread Scheduling Mechanism With Low-Power Register File for Mobile GPUsabstractIn response to the remarkable increase in 3D applications in consumer electronics devices in recent years, graphics processing units (GPUs) have become widely available on mobile devices. These GPUs typically use hardware multithreaded shaders to improve their throughputs for real-time rendering, but they depend on duplicate register files to maintain the context of each hardware thread, increasing power consumption. However, the register usage of shading programs is often relatively low, which causes many registers to remain unused, thus wasting power. Long latency memory operations can also consume unnecessary power to activate registers. This study proposes a low-power register file with multiple power modes to reduce the power consumption of the register file. This study also presents an adaptive thread scheduling mechanism to achieve a tradeoff between the power consumption of the register file and frames per second (FPS). Results show that the average performance degradation from the proposed low-power register file is only 0.62%. The proposed adaptive thread scheduling has average under prediction ratio of 3.32%. The leakage reduction of the proposed low-power register file is 74.80%. This reduction can be improved to 81.49%, 82.22%, and 84.28% with adaptive thread scheduling at frame rates of 30, 25, and 20, respectively. Chih-Chieh Hsiao, Slo-Li Chu, Chiu-Cheng Hsieh |
IEEE Trans. Multim. | 2 |
| 2013 | Energy-aware hybrid precision selection framework for mobile GPUs
Chih-Chieh Hsiao, Slo-Li Chu, Chen-Yu Chen |
Comput. Graph. | 2 |
| 2011 | A Dual-Mode Unified Shader with Frame-Based Dynamic Precision Adjustment for Mobile GPUsabstractIn order to extend the life for battery driven mobile devices and maintain image quality, this paper presents a dual-mode unified shader for mobile GPUs, which consists of floating-point and fixed-point SIMD shader, for high quality or energy-saving rendering. Furthermore, in order to increase the image quality in fixed-point rendering, this paper proposes a frame-based dynamic precision adjustment scheme to select appropriate precision for different 3D scenes. The proposed design has following characteristics: I) high quality rendering with floating-point and fixed-point rendering for energy saving, II) a frame-based dynamic precision adjustment scheme to select appropriate precision for given scene, III) a workload-based scene change detection mechanism to re-select precision in time. Furthermore, this paper presents side by side comparison on performance, power and image quality between floating-point and fixed-point rendering in real world 3D games. The results of proposed shader in real world 3D games have 48.6% reduction in dynamic power and 33% faster in thread execution for a shader under energy saving mode in average. Furthermore, the rendered image qualities under proposed dynamic precision are insensitive to human eyes and the PSNR outperform related work for 2.37% in average. This reveals a way to use conventional fixed-point with dynamic precision to implement low power unified shader with quality rendering for such power limited devices. Slo-Li Chu, Chih-Chieh Hsiao, Chen-Yu Chen |
EUC | 1 |
| 2011 | An Energy-Efficient Unified Register File for Mobile GPUsabstractThe programmability of mobile GPUs have raised in recently years, where the shaders inside are instructed by shading programs for realistic 3D effects. The register files for a conventional high throughput multithreaded shader consumes 10% to 20% energy of it. However the register usages of shading program are quite low. In order to reduce the dynamic energy for register file in a multithreaded mobile shader, this paper proposed an unified register file design to reduce both dynamic and leakage energy of it. The result shows that proposed design reduces 85% of dynamic energy in a multithreaded register file. Furthermore, the proposed design reduces 59% of leakage energy and 25% of area with negligible performance degradation. Also, the energy savings in proposed designs are at least 75% more than related work. Slo-Li Chu, Chih-Chieh Hsiao, Chiu-Cheng Hsieh |
EUC | 1 |
| 2010 | OpenCL: Make Ubiquitous Supercomputing PossibleabstractDue to the dramatic requirements of 3D games and applications, graphics processing unit (GPU) or general-purpose graphics processing unit (GPGPU) have become required components in the modern computer systems. While these devices enable high parallelism with huge amount of processing elements, the utilization of their capabilities in general scientific applications are still low due to their difficult programming paradigms. Therefore an open standard, OpenCL, is proposed to provide universal APIs and programming paradigms for various GPUs and accelerators. In this study, it adopts several benchmarks, with various computation characteristics, to demonstrate the capabilities of OpenCL with several platforms. These programs are parallelized by OpenMP and OpenCL, and then targeted on several GPUs and conventional servers. This paper also provides an example to illustrate the migration of the given program, from OpenMP to OpenCL. The presented experimental results show that these inexpensive GPUs will lead better performance than servers if adopt OpenCL paradigms. It will be the preliminary milestone of cheap supercomputing by the acceleration of GPUs that can be obtained ubiquitously. Slo-Li Chu, Chih-Chieh Hsiao |
HPCC | 1 |
| 2009 | Design a Hardware Mechanism to Utilize Multiprocessors on a Uni-processor Operating System
Slo-Li Chu, Chih-Chieh Hsiao, Pin-Hua Chiu |
ICA3PP | 1 |
| 2007 | Toward to Utilize the Heterogeneous Multiple Processors of the Chip Multiprocessor Architecture
Slo-Li Chu |
EUC | 1 |
| 2005 | An Energy Reduction Scheduling Mechanism for a High-Performance SoC Architecture
Slo-Li Chu |
EUC | 1 |
| 2004 | PSS: A Novel Statement Scheduling Mechanism for a High-Performance SoC Architecture
Slo-Li Chu |
ICPADS | 1 |
| 2004 | SAGE: an automatic analyzing system for a new high-performance SoC architecture--processor-in-memory
Slo-Li Chu, Tsung-Chuan Huang |
J. Syst. Archit. | 1 |
| 2004 | Improving workload balance and code optimization on processor-in-memory systems
Slo-Li Chu, Tsung-Chuan Huang, Lan-Chi Lee |
J. Syst. Softw. | 1 |
| 2003 | A statement based parallelizing framework for processor-in-memory architectures
Tsung-Chuan Huang, Slo-Li Chu |
Inf. Process. Lett. | 2 |
| 2001 | Improving Workload Balance and Code Optimization in Processor-in-Memory SystemsabstractPIM (Processor-In-Memory) architectures have been proposed in recent years. One major objective of PIM is to reduce the performance gap between the CPU and memory. To exploit the potential benefits of PIM, we designed a statement base parallelizing system-SAGE. In this paper, we extend this system to achieve better performance by devising several comprehensive optimizing techniques, which include IMOP (Intelligent Memory Operation) recognition, tiling for PIM, and a precise mechanism to get load-balanced execution schedule. The experimental results are also presented and discussed. Slo-Li Chu, Tsung-Chuan Huang, Lan-Chi Lee |
ICPADS | 1 |