This paper demonstrates a computational image sensor capable of implementing compressive sensing operations. Instead of sensing raw pixel data, this image sensor projects the image onto a separable 2-D basis set and measures the corresponding expansion coefficients. The inner products are computed in the analog domain using a computational focal plane and an analog vector-matrix multiplier (VMM). This is more than mere postprocessing, as the processing circuity is integrated as part of the sensing circuity itself. We implement compressive imaging on the sensor by using pseudorandom vectors called noiselets for the measurement basis. This choice allows us to reconstruct the image from only a small percentage of the transform coefficients. This effectively compresses the image without any digital computation and reduces the throughput of the analog-to-digital converter (ADC). The reduction in throughput has the potential to reduce power consumption and increase the frame rate. The general architecture and a detailed circuit implementation of the image sensor are discussed. We also present experimental results that demonstrate the advantages of using the sensor for compressive imaging rather than more traditional coded imaging strategies.

This paper discusses the application of a computational image sensor, capable of performing separable 2-D transforms on images in the analog domain, to compressive sensing. Instead of sensing and transmitting raw pixel data, this image sensor first projects the image onto a separable 2-D basis set. The inner products computed in these projections are computed in the analog domain using a computational focal-plane and a computational analog vector-matrix multiplier. Since this operation is performed in the analog domain, components such as the analog-to-digital converters can be taxed less when a only subset of correlations are performed. Compressed sensing theory prescribes the use of a pseudo-random, incomplete basis set, allowing for sampling at less than the Nyquist rate. This can reduce power consumption or increase frame rate.

This paper describes a floating-gate transistor based analog implementation of adaptive filters that adapt based on the least-mean-square (LMS) learning algorithm. Floating-gate transistors are used for both weight adaptation and non-volatile weight storage. A current-mode approach results in a compact, low-power synapse. Experimental results from a prototype chip with a matrix of 16times4 synapses along with supporting circuitry fabricated in a 0.35 mum CMOS process are provided to demonstrate adaptation.

This paper discusses a 256times256 computational imager capable of performing separable transforms. Unlike traditional imagers, this imager performs computation on-chip and in- pixel. The primary computation performed is a separable matrix transformation. Several developments were made since a previous matrix transform imager to expand functionality and resolution. New circuit design emphasized dynamic range, accuracy, and speed. This architecture includes a novel overlapping block scheme allowing 8times8 general separable 2-D convolutions as well as 16times16 block transforms.

In most reconfigurable systems, such as FPAAs and FPGAs, the switch element and its associated memory cell is a necessary overhead for performing computation with the active components. However, floating gate based switches in large-scale FPAAs can be programmed anywhere between simple "off" and "on" connections, which allows these programmable conductances to be used as computational elements within synthesized circuits. This decreases the notion of switches as computational dead weight and increases the potential computational area efficiency within FPAAs