George Matheou

dblp:77/10161 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 2019
0000-0002-3019-7102ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Parallel and multicore computing · 92% Processor architecture and microarchitecture · 4% Reconfigurable computing and FPGAs · 4%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › speculative parallelization
data-triggered threads
0.522017
Data-Driven Concurrency for High Performance Computing · ACM Trans. Archit. Code Optim. 2017
Architectural Support for Data-Driven Execution · ACM Trans. Archit. Code Optim. 2014
Parallel and multicore computing › parallel programming models
dataflow programming
0.312017
Data-Driven Concurrency for High Performance Computing · ACM Trans. Archit. Code Optim. 2017
Parallel and multicore computing
parallel programming models
0.312017
Data-Driven Concurrency for High Performance Computing · ACM Trans. Archit. Code Optim. 2017
Parallel and multicore computing › parallel computation models
data-driven execution
0.212014
Architectural Support for Data-Driven Execution · ACM Trans. Archit. Code Optim. 2014
Processor architecture and microarchitecture
chip multiprocessor
0.112014
Architectural Support for Data-Driven Execution · ACM Trans. Archit. Code Optim. 2014
Reconfigurable computing and FPGAs
FPGA prototyping
0.112014
Architectural Support for Data-Driven Execution · ACM Trans. Archit. Code Optim. 2014
Parallel and multicore computing
synchronization
0.112014
Architectural Support for Data-Driven Execution · ACM Trans. Archit. Code Optim. 2014

Methods — techniques the papers use, named apart from their topics

dynamic dataflow · 0.3data-driven multithreading · 0.3
YearPublicationVenuePosition
2019 Toward data-driven architectural support in improving the performance of future HPC architectures
George Matheou, Vassos Soteriou, Paraskevas Evripidou
Parallel Comput.1
2017 Data-Driven Concurrency for High Performance Computing
abstract
In this work, we utilize dynamic dataflow/data-driven techniques to improve the performance of high performance computing (HPC) systems. The proposed techniques are implemented and evaluated through an efficient, portable, and robust programming framework that enables data-driven concurrency on HPC systems. The proposed framework is based on data-driven multithreading (DDM), a hybrid control-flow/dataflow model that schedules threads based on data availability on sequential processors. The proposed framework was evaluated using several benchmarks, with different characteristics, on two different systems: a 4-node AMD system with a total of 128 cores and a 64-node Intel HPC system with a total of 768 cores. The performance evaluation shows that the proposed framework scales well and tolerates scheduling overheads and memory latencies effectively. We also compare our framework to MPI, DDM-VM, and OmpSs@Cluster. The comparison results show that the proposed framework obtains comparable or better performance.
George Matheou, Paraskevas Evripidou
ACM Trans. Archit. Code Optim.1
2014 Architectural Support for Data-Driven Execution
abstract
The exponential growth of sequential processors has come to an end, and thus, parallel processing is probably the only way to achieve performance growth. We propose the development of parallel architectures based on data-driven scheduling. Data-driven scheduling enforces only a partial ordering as dictated by the true data dependencies, which is the minimum synchronization possible. This is very beneficial for parallel processing because it enables it to exploit the maximum possible parallelism. We provide architectural support for data-driven execution for the Data-Driven Multithreading (DDM) model. In the past, DDM has been evaluated mostly in the form of virtual machines. The main contribution of this work is the development of a highly efficient hardware support for data-driven execution and its integration into a multicore system with eight cores on a Virtex-6 FPGA. The DDM semantics make barriers and cache coherence unnecessary, which reduces the synchronization latencies significantly and makes the cache simpler. The performance evaluation has shown that the support for data-driven execution is very efficient with negligible overheads. Our prototype can support very small problem sizes (matrix 16×16) and ultra-lightweight threads (block of 4x4) that achieve speedups close to linear. Such results cannot be achieved by software-based systems.
George Matheou, Paraskevas Evripidou
ACM Trans. Archit. Code Optim.1