In order to meet the diverse requirements of modern storage systems, flash memory should be optimized by precisely tuning a huge number of internal operating parameters. Although 3D NAND flash memory successfully increases the capacity of storage systems, its complex architecture and unique error behavior make such optimization a more difficult and time-consuming process during NAND manufacturing. This work introduces Norns, a novel method for post-fabrication optimization of NAND flash memory, which is an essential step in the manufacturing process of modern 3D NAND flash memory to simultaneously meet various requirements on reliability, performance, yield, etc. Norns is based on simple machine-learning approaches yet with three key guidelines that leverage (i) domain-specific rules, (ii) recent optimization results, and (iii) online simulation, respectively, to enable quick optimization of a large number of device parameters within the limited product turnaround time (TAT). We evaluate Norns in mass production for 7th-generation QLC NAND flash memory and 8th-generation TLC NAND flash memory. Our Norns can achieve superior optimization over existing post-fabrication optimization techniques by showing significant performance and reliability improvements by up to 8.8% and 12% on average, respectively.

With the growing complexity of integrated circuits and increasing capacity of memory devices, it is becoming increasingly difficult to screen out all defective dies through wafer test. To address this problem, statistical methods are being increasingly applied on test data to screen out potential defective dies. Among such methods, the good-die-in-bad-neighborhood (GDBN) method is effective. Most GDBN methods use the bin data of nearby dies through Cartesian coordinates. However, the bin data provide only binary information, and Cartesian coordinates do not fully reflect the spatial correlations of wafers. Therefore, this paper proposes a novel GDBN method using bad block data, which are key indicators of the in-field failure of NAND flash memory. The defect risk is predicted through statistical kernel smoothing based on Cartesian and polar coordinates to consider the spatial correlations in various environments of wafer fabrication. Experiments on NAND flash products show that the in-field failure classification performance of the proposed method, in terms of the area under the curve value, is 30% higher than that of the existing method, based on the bin data and Cartesian coordinates.

The decreasing lifetime of NAND flash memory, as a side effect of recent advanced semiconductor process scaling, is emerging as one of major barriers to the wide adoption of SSDs in high-performance computing systems. In this paper, we propose Dynamic Erase Voltage and Time Scaling (DeVTS), an integrated approach to extend the lifetime (particularly, endurance) of NAND flash memory. DeVTS is motivated by our key observation that erasing a NAND block with a lower voltage or at a slower speed can significantly improve NAND endurance. However, using a lower erase voltage causes adverse side effects on the write performance and retention capability of NAND flash memory. In order to improve NAND endurance without affecting the other NAND requirements, we take advantage of idle times between write requests and variations of the retention requirement when writing data to a NAND block erased with a lower voltage. We have implemented a DeVTS-aware FTL, called dvsFTL, which exploits the tradeoff relationship between the endurance and erase voltages/times by accurately predicting the write performance and retention requirements. Our experimental results show that dvsFTL can improve NAND endurance by 94 percent, on average, over an existing DeVTS-unaware FTL while all the NAND requirements are preserved.

We propose a new system-level solution that improves both the performance and lifetime of NAND storage systems by exploiting the performance asymmetry of NAND devices. At the device level, we propose a new program sequence, called relaxed program sequence (RPS), which allows more flexible page allocations in a block without compromising NAND reliability. By combining RPS with per-block parity pages, we can improve the write bandwidth and eliminate expensive paired page backup operations. Experimental results show that the proposed technique can increase IOPS by up to 56% and reduce the number of block erasures by up to 30% over an existing RPS-oblivious FTL.

The read-disturb problem is emerging as one of the main reliability issues in high-density NAND flash memory. A read-disturb error, which causes data loss, occurs to a page when a large number of reads are performed to its neighboring pages. In this paper, we propose a novel integrated approach for managing the read-disturb problem. Our approach is based on our key observations from the NAND physics that the read disturbance to neighboring pages is a function of the read voltage and the read time. Since the read disturbance has an exponential dependence on the read voltage, lowering the read voltage can improve the read-disturb resistance of a NAND block. By modifying NAND chips to support multiple read modes with different read voltages, our approach allows a flash translation layer module to exploit the tradeoff between the read disturbance and write speed. Since the read disturbance is also proportional to the read time, our approach exploits the difference in the read time among different NAND pages so that frequently read pages can be less intensively read-disturbed using fast page reads. By intelligently relocating read-intensive data to read-disturb resistant blocks and pages, our approach can reduce a large portion of the time overhead from managing read-disturb errors. We also propose a proactive data migration technique which is effective in reducing large variations in I/O response times of the existing on-demand read reclaim (RR) technique. Our experimental results show that our proposed techniques can reduce the execution time overhead by 73% over the existing read-disturb management technique while reducing I/O response time fluctuations during RR activations.