A hybrid signed convolution module with the architecture of an unsigned divide-and-conquer (UDC) multiplier is proposed to improve the functional diversity and energy efficiency of artificial intelligence (AI) accelerators based on spin-transfer-torque magnetic random access memory (STT-MRAM). The proposed UDC multiplier framework enables three multiplication modes ($n \times n$,$n \times n$/2, and$n/2\times n$/2 bit), considerably enhancing the multiplier’s versatility for next-generation AI accelerators. Compared to the state-of-the-art convolution accelerators, the UDC multiplier-based convolution module offers the lowest average power consumption for$8\times8$bit convolution. By deploying power-gating technology on STT-MRAM, the proposed convolution module preserves sufficient accuracy in high-bit multiplication while decreasing energy consumption by a factor of 22. Furthermore, incorporating a hybrid convolution module improves power efficiency by an additional$8\times $, culminating in a$175\times $decrease in power efficiency for an STT-MRAM-based AI accelerator.

In the above article[1], the reference numbers [10], [11], [12], and [13] inTable IIwere not correct and should be changed to [11], [12], [13], and [14]. The correctTable IIis illustrated as follows.

Offloading the unprecedented growing data to the edge exhibits a mainstream trend in the Industrial Internet of Things (IIoT) era, delivering far-reaching impacts in all aspects of our daily lives, including transportation, health care, and entertainment. However, voluminous data analyzes and processing at the edge will unavoidably raise the edge processor's burden and dramatically expand its design complexity and energy dissipation. This article proposes a flexible bit-adjustment-based energy-efficient convolution module with an approximate divide-and-conquer (ADC) multiplier for compact and low-power edge processor design. The maximum distribution search technique is utilized to exploit the optimal fixed-point representation format for both input and output of the convolution module. The neural network manifests the same precision as a 32-b floating-point multiplication deploying the determined representation formats. An ADC multiplier is proposed to realize the convolution module by eliminating the high-bit multiplication between weights and feature maps. The dynamic power consumption of the ADC multiplier-based convolution module with the$Q(6, 9)$input and$Q(7, 8)$output representation formats is 3.85% lower than that of the 16-b signed multiplication circuit. Furthermore, the dynamic power consumption with$Q(6, 9)$input is capable of being decreased by 15.38% for the 16-b convolution if the output is represented by the$Q(1, 14)$format and by up to 39.93% for the 64-b multiplication. The practical verification system of the convolution module working on a field-programmable gate array evaluation board exhibits an outstanding low-power characteristic.

This paper describes a new hierarchical design method for large scale and high-performance LSIs, which eliminates the need to perform budgeting. The budgeting step in hierarchical design partitions the total propagation time constraint for a path between any two flip-flops (FFs) in different hierarchical blocks into budgets for the different segments of the path that lie within different blocks. In practice, budgeting may result in the need for additional iterations of the synthesis and physical design flow, or may achieve sub-optimal results in terms of area, power, or clock frequency. The proposed method makes the design process budgeting-free by moving the borders of the hierarchical blocks so that all borders of the hierarchical blocks are FFs. For a commercial 500 MHz LSI with 141 million transistors, the design team required 2 months to archive the target frequency through try-and-try-again budgeting, while our budgeting-free method produced a design that meets the performance target within days.

This paper describes a new hardware/software co-verification method for System-On-a-Chip, based on the integration of a C/C++ simulator and an inexpensive FPGA emulator. Communication between the simulator and emulator occurs via a flexible interface based on shared communication registers. This method enables easy debugging, rich portability, and high verification speed, at a low cost. We describe the application of this environment to the verification of three different complex commercial SoCs, supporting concurrent hardware and embedded software development. In these projects, our verification methodology was used to perform complete system verification at 0.2-1.1 MHz, while supporting full graphical interface functions such as "waveform" or "signal dump" viewers, and debugging functions such as "step" or "break".

Article Free Access Share on Timing optimization on mapped circuits Authors: Ko Yoshikawa NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, Japan NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, JapanView Profile , Hiroshi Ichiryu NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, Japan NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, JapanView Profile , Hisato Tanishita NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, Japan NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, JapanView Profile , Sigenobu Suzuki NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, Japan NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, JapanView Profile , Nobuyoshi Nomizu NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, Japan NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, JapanView Profile , Akira Kondoh NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, Japan and NEC Engineering Corp. NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, Japan and NEC Engineering Corp.View Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 112–117https://doi.org/10.1145/127601.127639Published:01 June 1991Publication History 17citation216DownloadsMetricsTotal Citations17Total Downloads216Last 12 Months12Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF