The poor quality of the die stacking process for 3-D integrated circuits can result in the failure of the process in the through-silicon-vias (TSVs) in dense regions. Previous works use the same number of redundant TSVs and architectures that do not consider the TSV density. A repair architecture and an appropriate number of redundant TSVs, which are chosen considering the TSV density, are required for an improved repair rate. This paper proposes a method that demonstrates such an architecture and calculates the required number of TSVs. The method has a high repair rate for clustered faults, and wire-length problems are solved using the shift-based repair method.

A chain-based coupling delay estimation method for through-silicon-vias (TSVs) in 3-D integrated circuits is proposed. Existing works target the worst case scenarios and this leads to inaccurate TSV coupling delay estimations, as the worst case may not occur during normal operation. The proposed method calculates the TSV coupling delay using simulation-based switching data. In addition, our TSV chain method allows us to capture the effects of nonneighboring TSVs accurately. Our simulations show that the error introduced by our method without using HSPICE is less than 10 ps even in TSV-crowded regions.