Spike timing dependent plasticity (STDP) is an important neural process that enables biological neural networks to learn by strengthening or weakening synaptic connections between neurons. This work presents simulation results and post-silicon experimental data that demonstrate for the first time the possibility of tuning the on state resistance of a type of emerging resistive memory device known as conductive bridge random access memory (CBRAM) in accordance with the biological STDP rule for neuromorphic applications. STDP behavior is demonstrated for CBRAM devices integrated with CMOS spiking neuron circuitry through back end of line post-processing for different initial resistance values and spike durations.

In this paper, we present a review of the state of the art in memristor technologies. Along with ionic conducting devices [i.e., conductive bridging random access memory (CBRAM)], we include phase change, and organic/organo-metallic technologies, and we review the most recent advances in oxide-based memristor technologies. We present progress on 3-D integration techniques, and we discuss the behavior of more mature memristive technologies in extreme environments.

Discrete and embedded nonvolatile memory (NVM) technologies have been an integral part of electronic systems for the past 25 years. In recent years, the proliferation of personal media devices such as multimedia-enabled cell phones, personal music players, and digital cameras has accelerated the adoption of silicon-based solid state storage cards in consumer markets. Despite the expanded use of nonvolatile memory technologies in a variety of integrated systems, little has changed with respect to the core technology and cells that hold the data when power has been turned off. Today, floating gate (FG) or oxide-nitride-oxide trapped charge (ONO) cell structures dominate as the core technology behind all NVM devices and embedded blocks. All of the nonvolatile memory devices in production today based on these technologies require high voltage in excess of 5-8 V to operate primarily due to the fundamental nature of core cells and the physics of charge storage mechanisms. These are huge overvoltage requirements considering that the transistors in the logic block require substantially lower voltages (e.g., sub-65 nm logic CMOS operate at less than 1 V). Integrating such high-voltage operation in advanced logic processes such as 65 nm or below logic CMOS process is yet another challenge limiting the exploitation of NVM for low-power embedded applications. The high voltage requirement for operation of these core cells has put strains on the continued scaling of today's discrete and embedded NVM technologies. Furthermore, future ultralow-power and subthreshold CMOS applications such as energy starved electronics require operations at sub-500 mV which clearly set forth significant challenges in integrating today's NVM technologies as nonvolatile storage elements for such systems. Several emerging technologies are competing to become the building blocks of next-generation nonvolatile memory solutions. Each of these emerging technologies has unique characteristics in terms of physical scaling, voltage scaling, cost, performance, and power features which differ from today's FG and ONO based technologies. This paper reviews the fundamental characteristics of current nonvolatile memory technologies as well as several promising emerging technologies from energy and power perspectives and specifically discusses the suitability of each one for use in ultralow-power and subthreshold CMOS applications.

A novel technique has been developed for the fabrication of Si quantum dot structures with controllable electron number through both top and side gates. We have tested devices ranging in size from 40 to 200 nm. By varying the density with the top gate, and controlling the input and output barriers of the dot with the side gates, conductance peaks are observed which map details of the energy level within the dot as well as the interaction of the electrons with one another.