This paper presents the design and implementation of a miniaturized, low-noise Magnetic Tunnel Junction (MTJ)-based proximity sensor with a high-performance readout channel. The MTJ-based proximity sensor consists of 1102 circular pillars of 100um diameter arranged in series, providing accurate detection of subtle interactions, such as a finger approaching the sensor. The system exhibits a 54 dB gain and a bandwidth of 1 kHz, with a noise power density of less than 30 nV/√Hz at 100 Hz, ensuring high precision. The proximity sensor demonstrated linear behavior for distances from 18 mm to 45 mm, with a sensitivity sufficient to detect low magnetic field variations. Experimental validation of the sensor shows a high degree of accuracy (R2= 0.9715), confirming its potential for use in touchless control, mobile technology, and industrial applications.

This paper presents a novel approach to reservoir computing (RC) using Granular Vortex-Based Magnetic Tunnel Junctions (GV-MTJs) for temporal applications. GV-MTJs, with their unique magnetic domain configurations and granular structures, provide the necessary fading memory and non-linear dynamics essential for RC. The vortex core’s oscillatory motion within the device allows for temporal correlation of inputs, giving fading memory, while grain-induced non-linear resistance and frequency variations enhance data dimensionality. Our findings indicate that varying device parameters can affect the relaxation time and gyrotropic frequency in both simulation and experiments. Relaxation times range from 100-140 ns and frequencies from 250-100 MHz. Through experiments, the classification error was reduced by 27% for the best sample, others showed limited potential. Due to signal application speed constraints, the fading memory is not fully utilized. However, the inherent RC capabilities of GV-MTJs are validated. This paper highlights the promise of GV-MTJs in neuromorphic computing and suggests avenues for future research to optimise their use in practical applications.

With the rapidly evolving internet of things (IoT) era, the ever-rising demand for data transfer and storage has put a knotty problem on conventional computers, known as the von Neumann bottleneck and memory wall problem. Slow scaling of CMOS transistors due to physical and economical limitations further exacerbates the situation. It is only logical to mimic what has been known so far as the most energy-efficient system, the human brain. The brain-inspired neuromorphic computing systems compute and store the data locally, which dramatically reduces area and energy consumption. In this work, we demonstrate thermal-induced multi-state memristors for neuromorphic engineering applications. We show that in a neural network that uses a memristor-spintronic nano oscillator connection to implement the synapse-neuron pair, with increased temperature, the total power consumption could be reduced by more than 50 % without degrading the output power of a spintronic-based neuron.

Many classification applications rely on real-time processing and detection of RF signals at high frequencies. RF signal sampling requires sophisticated hardware, i.e., broadband analog front-ends and high-speed analog-to-digital converters according to the well-known Shannon-Nyquist theorem. Such devices either are expensive or suffer from limited detection bandwidths and sampling rates. Here, we proposed a novel spintronic-based classification front-end for real-time analysis and classification of RF signals. In comparison to the conventional CMOS-based systems, the proposed system can increase the classification speed dramatically while consuming an order of magnitude less power.

Spintronic nano-devices have shown great potential to reduce the energy consumption of neuromorphic computing systems (NCSs). In the spintronic-based NCSs, the switching or oscillation of a magnetic tunnel junction (MTJ) is a common approach to mimic neuron firing. However, still there is a gap between the performance (operation/sec/Watt/cm 2) of the human brain and NCSs. To mitigate this gap, it is essential to further decrease the energy consumption and the delay of the NCS. The high-energy consumption of the MTJ-based NCS is mostly related to the high current needed to switch the MTJ state. Hence, some previous methods tried to perform real-time tracking of the MTJ state by monitoring the voltage across the MTJ and cut off its current immediately after switching. However, due to the small voltage changes after switching, these methods suffer from high-power consumption. In this article, a new method based on the tracking of the MTJ current (instead of its voltage) and terminating the MTJ current after switching is proposed. Due to the large changes in the MTJ current after switching (about 40%), there is no need to use an amplifier in the proposed common-mode tracking and terminating circuit (CM-TTC). The simulation results in 65-nm CMOS technology confirm that the proposed CM-TTC technique can improve the energy consumption and speed of a typical NCS by 53% and 2X. Moreover, the power consumption, delay, and area overhead of CM-TTC is reduced by 12.8%, 73%, and 95% compared with the best state-of-the-art track and termination circuits.

In this paper, a 3-bit hybrid spin-CMOS Flash analog to digital converter (ADC) is developed, which works based on switching of perpendicular-anisotropy magnetic tunnel junctions (p-MTJs) using both spin Hall effect (SHE) and spin-transfer torque (STT). The structure consists of unconnected p-MTJs in which heavy metals (HMs) are implemented with different cross-sectional areas leading to devices with different critical current (IC) values. ICvalues act as reference currents (Iref) eliminating the need for transistors with different sizes creating various values of Iref. Moreover, the power-hungry comparators in complementary metal-oxide-semiconductor (CMOS) Flash ADC can be replaced with p-MTJs because they compare the input current (Iin) with their IC. Hence, this approach can reduce the chip area and the mismatch issue as compared to the conventional CMOS Flash ADC. In this structure, a copy of Iin passes through the HM of each p-MTJ, which improves the tunnel magnetoresistance (TMR) and as a results increasing the reading reliability, linearity, and speed of spin Hall-based ADCs with attached HMs. The simulation results in 180nm CMOS technology show 845 μW of power consumption at 200 MS/s with the differential nonlinearity (DNL) and integral nonlinearity (INL) of -0.149 LSB (least significant bit) and 0.085 LSB, respectively.

Neuromorphic computing could pave the way to a new generation of smart sensors that can process signals locally through Spiking Neural Networks (SNNs). For this paradigm to take hold, it is necessary to have an analog-to-spike encoder adaptable to a wide range of applications. The encoding system should offer the possibility to try different encoding algorithms, giving freedom to the designers to select the most appropriate approach for the target task. At the same time, it should feature a tunable parameter to modulate the spike density, in the pursuit of a compromise between accuracy and power consumption. Therefore, the goal of this work is to provide a platform enabling the conversion of analog signals to a sequence of spikes, characterized by flexibility, high energy efficiency, and small area. We introduce an encoder designed and simulated in a standard 0.18 μ-m CMOS process which benefits from a switch- capacitor and a dynamic comparator to achieve very high energy efficiency. The controller unit can switch between Slope-based or Step-Forward Encoding algorithms. The encoder consumes 30 fJ/spike at 1.5 V supply voltage and occupies an area of 0.00325 mm2.

This paper presents a novel low-power Tunneling Field-Effect-Transistor (TFET) 8T-SRAM cell. The proposed cell uses a supply feedback to improve its stability. The new structure at the supply voltage of 300 mV, compared to the conventional 6T SRAM, shows 33% and 26% improvements in Read Static Noise Margin (RSNM), and write margin (WM), respectively. Layout drawn in 32-nm technology shows that the proposed 8T cell offers 1.2X larger area overhead compared to the conventional 6T cell, however with considering of higher performance and stability of the proposed design at low supply voltages, this is worthy of use. Also, proposed design shows better performance under process variations compared to the 8T-SRAM cell designed using other technologies.

Spin-transfer torque random access memory (STT-RAM) has emerged as an attractive candidate for future nonvolatile memories. It advantages the benefits of current state-of-the-art memories including high-speed read operation (of static RAM), high density (of dynamic RAM), and nonvolatility (of flash memories). However, the write operation in the 1T-1MTJ STT-RAM bitcell is asymmetric and stochastic, which leads to high energy consumption and long latency. In this paper, a new write assist technique is proposed to terminate the write operation immediately after switching takes place in the magnetic tunneling junction (MTJ). As a result, both the write time and write energy consumption of 1T-1MTJ bitcells improves. Moreover, the proposed write assist technique leads to an error-free write operation. The simulation results using a 65-nm CMOS access transistor and a 40-nm MTJ technology confirm that the proposed write assist technique results in three orders of magnitude improvement in bit error rate compared with the best existing techniques. Moreover, the proposed write assist technique leads to 81% energy saving compared with a cell without write assist and adds only 9.6% area overhead to a 16-kbit STT-RAM array.

In this brief, a new write assist technique is proposed to improve the write characteristics of 1T-1 magnetic tunnel junction (MTJ) spin-torque transfer memory bitcell through a symmetric write operation. This is done by applying a negative voltage to the bitline during write 1 operation. The proposed technique is compared with the best previously proposed techniques. The simulation results using 65-nm CMOS technology show that the proposed write assist technique results in 19% improvement in write energy compared with the boosted wordline (BWL) technique. In addition, the proposed write assist technique leads to 12% and 48% bitcell area reduction compared with BWL and balanced write techniques, respectively. Furthermore, the maximum voltage across the MTJ is reduced by 20% and 6% compared with BWL and balanced write techniques, respectively.

Spin-transfer torque random access memory (STT-RAM) has emerged as an attractive candidate for future non-volatile memories. However, the write operation in 1T-1MTJ STT-RAM bit-cells is asymmetric and stochastic which leads to high energy consumption and long latency. In this paper, a new write assist technique is proposed to terminate the write operation immediately after switching takes place in the MTJ. As a result, both write time and write power of 1T-1MTJ bit-cells improve. Moreover, the proposed write assist technique is robust in the presence of process variations. Simulation results using 65nm CMOS access transistor and 40-nm magnetic tunneling junction technology confirm that the proposed write assist technique results in three orders of magnitude improvement in bit error rate compared with the best existing techniques. Moreover, the proposed write assist technique leads to 81% power savings compared with a cell without write assist.

Fully digital analog to digital converters (FD-ADC) have potential applications in very low power ICs and can be implemented in digital CMOS technology. In this paper the non-linearity of the delay element (DE), which is the main building block in an FD-ADC, is discussed and its impact on the overall performance of the ADC is addressed. It is shown that the non-linearity of the delay element should be within certain limits in order to achieve the best signal to noise plus distortion ratio (SNDR). Also, a new current starved delay element with enhanced linearity is proposed. Using the proposed DE, the SNDR of a 6-bit FD-ADC is improved by 7dB.