In advanced CMOS technology, the NBTI (negative bias temperature instability) effect results in delay degradations of PMOS transistors. Further, because of clock gating, PMOS transistors in a clock tree often have different active probabilities, leading to different delay degradations. If the degradation difference is not properly controlled, this clock skew may cause the circuit fails to function at some point later in time. Intuitively, the degradation difference can be eliminated, if we increase the active probability of the low-probability clock gates to ensure the clock gates at the same level always having the same active probability. However, this intuitive method may suffer from large power consumption overhead. In this article, we point out, by carefully planning the transistor-level clock signal propagation path, we can have many clock gates whose active probabilities do not affect the degradation difference. Based on that observation, we propose a critical-PMOS-aware clock tree design methodology to eliminate the degradation difference with minimum power consumption overhead. Benchmark data consistently show our approach achieves very good results in terms of both the NBTI-induced clock skew (i.e., the degradation difference) and the power consumption overhead.

Due to clock gating, the PMOS transistors in the clock tree often have different active probabilities, which lead to different NBTI delay degradations. To ensure that the clock skew is always zero, there is a demand to eliminate the degradation difference. In this paper, we present a critical-PMOS-aware clock tree design methodology to deal with this problem. First, we prove that, under the same tree topology, the NAND-type-matching clock tree has the minimum number of critical PMOS transistors. Then, we propose a 0–1 ILP (integer linear programming) approach to minimize the power consumption overhead while eliminating the degradation difference. Benchmark data consistently show that our design methodology can achieve very good results in terms of both the clock skew (due to the degradation difference) and the power consumption overhead.

In a synchronous sequential circuit, huge current peaks are often observed at the moment of clock transition (since all registers are clocked). Previous works focus on reducing the number of switching registers. However, even though the switching registers are the same, different combinations of switching directions still result in different peak currents. Based on that observation, in this article, we propose an ECO (engineering change order) approach to minimize the peak current by considering the switching directions of registers. Our approach is well suitable for reducing the peak current in IC testing. Experimental data consistently show that our approach works well in practice.

Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR gates, and buffer gates. If the logic gates at the same level are in different types, which have different timing behaviors, the control of clock skew becomes difficult. Based on that observation, in this paper, we present a novel clock tree design style, called type-matching clock tree, to ensure that the logic gates at the same level are in the same type. We prove that any clock control logic can always be transformed to our type-matching clock tree. Then, based on the idea of type-matching clock tree, we propose a zero skew gated clock tree synthesis algorithm. Compared with the industry-strength gated clock tree synthesis, experimental data show that our approach can significantly reduce the clock skew in every process corner with a small penalty on the clock tree area and the clock tree power consumption.

The combination of clock skew scheduling and delay insertion may lead to further clock period reduction. Although some previous works can minimize the clock period, they only heuristically reduce the required inserted delay. However, since the delay insertion is an ECO (engineering change order) process, minimizing the required inserted delay is very important for the design closure, In this paper, we present a linear program to formally formulate the simultaneous application of clock skew scheduling and delay insertion. Our objective is not only to achieve the lower bound of the clock period, but also to achieve the lower bound of required inserted delay. Compared with previous works, our paper has the following two significant contributions: (1) our approach is the first work that guarantees solving this problem optimally; and (2) our paper is the first proof of showing that the time complexity of this problem is polynomial.

Given several specific clocking domains, the peak current minimization problem can be formulated as a 0-1 integer linear program. However, if the number of binary variables is large, the run time is unacceptable. In this paper, we study the reduction of this high computational expense. Our approach includes the following two aspects. First, we derive the ASAP schedule and the ALAP schedule to prune the redundancies without sacrificing the exactness (optimality) of the solution. Second, we propose a zone-based scheduling algorithm to solve a large circuit heuristic ally.

In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the reduction of switching activities of state registers (i.e., state bits). However, even though the switching state registers are the same, different combinations of switching directions still result in different peak currents. Based on that observation, in this paper, we propose the first approach to re-encode an FSM by considering the switching directions of state registers in order to minimize the peak current caused by the state transition. Experimental data consistently show that the peak current is reduced with no penalty.