We consider the design of convolutional codes and low density parity check (LDPC) codes with minimum-shift keying (MSK) when the receiver employs iterative decoding and demodulation. The main idea proposed is the design of coded schemes that are well matched to the iterative decoding algorithm being used rather than to hypothetical maximum-likelihood decoding. We first show that the design is crucially dependent on whether the continuous phase encoder (CPE) is realized in recursive form or in nonrecursive form. We then consider the design of convolutionally coded systems and low density parity check codes with MSK to obtain near-capacity performance. With convolutional codes, we show that it is possible to improve the performance significantly by using a mixture of recursive and nonrecursive realizations for the CPE. For low density parity check codes, we show that codes designed for binary phase shift keying are optimal for MSK only if the nonrecursive realization is used; for the recursive realization, we design new LDPC codes based on the concept of density evolution. We show that these codes outperform the best known codes for MSK and have lower decoding complexity.

We investigate serial concatenation of low-density parity check (LDPC) codes and minimum shift keying (MSK) with iterative decoding. We show that the design of LDPC codes is crucially dependent on the realization of the MSK modulator. For MSK modulators with nonrecursive continuous phase encoders (CPEs), optimal codes for BPSK are optimal, whereas for MSK modulators with recursive CPEs, the BPSK codes are not optimal. We show that for nonrecursive CPEs, iterative demodulation and decoding is not required even though the CPE has memory. However, iterative demodulation is essential for recursive CPEs. For recursive CPEs, we design LDPC codes using density evolution and differential evolution considering iterative demodulation and decoding. The resulting codes provide significantly improved performance over the existing codes.

Issues associated with the integration of transceiver components on to a single silicon substrate are discussed. In particular, recently proposed receiver and transmitter architectures for high integration are examined on the promise of providing multistandard capability. In addition, existing barriers to lower power transceiver operation are examined as well as some proposed directions for future integrated transceiver research and development.