Theoretical analysis and experimental results for a DPSK system with nonredundant error correction are described. The error correction capability of the proposed demodulation method is achieved without utilizing additional bandwidth. The demodulator utilizes outputs of differentially coherent detectors that employ the received signal delayed by two or more time slots as references. These outputs are shown to be the parity check sums of two or more conSecutive outputs of the conventional detector under noise-free conditions. The error rate performance of the proposed demodulation method is theoretically and experimentally studied for quaternary DPSK. Experimental results agree with the theory, which indicates that performance is superior to conventional DPSK by 1.2 dB, but poorer than coherent detection by 1.3 dB. This method can be applied effectively to TDMA communications and to on-board regenerative repeaters.

The experiment we conducted for integrated digital satellite communications is aimed at realizing integrated services digital networks by satellite communication. The experiment was carried out in 1980 using the Japanese experimental communication satellite "CS." This experiment uses 30/20 GHz small earth stations and demand-assignment time-division multiple-access (TDMA) systems. Communications between customer terminals, which contain video conferencing, high-speed facsimile communication, high-speed computer communication, and packet-switching signal transmission, were carried out through the experimental digital satellite link. This paper describes the configuration of the experimental integrated digital satellite communications system and the experimental results of communications between customer terminals.

In a high-speed digital radio relay system with four-phase-shift keying and coherent detection, it is very important to realize an accurate, stable, and wide-band carrier synchronizer. In this paper, the influence of time delay causing trouble for the wide-band synchronizer realization is analyzed. Then the design procedure of this synchronizer is described. Finally, the realizability of such a synchronizer is proved by the experimental results at a 1.7-GHz intermediate frequency and a 200-MHz clock frequency.