Sparse computations are common in practical HPC, AI and graph-based applications. Such computations often exhibit scattered and fragmented data accesses, which negatively impact data transfer efficiency to/from accelerators. We propose, implement and evaluate an algorithm for extracting or mining sparsity patterns that exist in sparse matrices. The algorithm extracts multiple pattern types in a matrix, including blocks, bands, triangles or regular compositions of each. It does so without a priori knowledge of the presence of these patterns in the matrix. The patterns may contain, under user control, zero elements, or imperfections, to facilitate the extraction of larger patterns. Additionally, we introduce the Compressed Sparse Pattern (CSP), a novel compressed representation for sparse matrices that is based on these patterns. The use of CSP combined with extensions to Address Generation Units (AGUs) of accelerators regularize data accesses and improve data transfer efficiency. Evaluation of the pattern mining algorithm and CSP using 26 real-world sparse matrices is conducted on an Ubuntu system with an 8 core Intel CPU (3.6 GHz i7-9700K) and 32 GB of memory. The evaluation shows that patterns of different sizes and shapes are common, representing ∼82% of the non-zero elements in these matrices. The patterns can be efficiently extracted in time, with an average of 4.6 seconds. The evaluation also shows that the mining of composite patterns contributes ∼8% to the number of non-zeros in patterns and that imperfections increase pattern sizes with a minimal impact of only ∼7% zero elements in patterns. Finally, using CSP leads to up to 90% reduction in data transfer overhead, compared to CSR and CSC, both common compressed sparse matrix representations. These results validate our approach of extracting and representing patterns to improve data transfer efficiency.

To guide practitioners and researchers to design and research Machine Learning (ML) system development processes, we conduct a preliminary literature review on ML system development practices. We identified seven papers and two other papers determined in an ad-hoc review. Our findings include emphasized phases in ML system developments, frequently described ML-specific practices, and tailored traditional practices.

Business-to-Business (B-to-B) software development companies develop services to satisfy their customers’ requirements. Developers should prioritize customer satisfaction because customers greatly influence agile software development. However, satisfying current customer’s requirements may not fulfill actual users or future customers’ requirements because customers’ requirements are not always derived from actual users. To reconcile these differences, developers should identify conflicts in their strategic plan. This plan should consider current commitments to end users and their intentions as well as employ a data-driven approach to adapt to rapid market changes. A persona models an end user representation in human-centered design. Although previous works have applied personas to software development and proposed data-driven software engineering frameworks with gap analysis between the effectiveness of commitments and expectations, the significance of developers’ commitment and quantitative decision-making are not considered. Developers often do not achieve their business goal due to conflicts. Hence, the target of commitments should be validated. To address these issues, we propose Data-Driven Persona Retrospective (DDR) to help developers plan future releases. DDR, which includes the Persona Significance Index (PerSI) to reflect developers’ commitments to end users’ personas, helps developers identify a gap between developers’ commitments to personas and expectations. In addition, DDR identifies release situations with conflicts based on PerSI. Specifically, we define four release cases, which include different situations and issues, and provide a method to determine the release case based on PerSI. Then we validate the release cases and their determinations through a case study involving a Japanese cloud application and discuss the effectiveness of DDR.

A Digital Annealer (DA) is a dedicated architecture for high-speed solving of combinatorial optimization problems mapped to an Ising model. With fully coupled bit connectivity and high coupling resolution as a major feature, it can be used to express a wide variety of combinatorial optimization problems. The DA uses Markov Chain Monte Carlo as a basic search mechanism, accelerated by the hardware implementation of multiple speed-enhancement techniques such as parallel search, escape from a local solution, and replica exchange. It is currently being offered as a cloud service using a second-generation chip operating on a scale of 8,192 bits. This paper presents an overview of the DA, its performance against benchmarks, and application examples.

In this paper, we propose an FPGA-accelerated data optimization system for high-speed data transfer via Wide Area Network (WAN). To maintain high quality in cloud services, high-speed transfer among data centers via WAN is important. To accelerate transfers via WAN, data optimization techniques are used to reduce the size of the data transmitted to the WAN. Compression and deduplication are widely-used data optimization techniques; data sent is shrunk before transmission and restored upon receipt. However, the computational time of these techniques is so great that it is difficult to achieve high performance using only a CPU. To solve this problem, we developed an efficient data optimization system using both CPU and FPGA. We designed a dedicated accelerator whose architecture is suitable for each processing characteristic of data optimization. We also proposed an efficient data flow inside the FPGA and communication method between the CPU and the FPGA. Thanks to the appropriate pipelining and parallelization, and the data flow, the measured throughput of our developed accelerator achieves over 41 Gbps. With this accelerator, we can realize a data transfer system whose throughput is 40 Gbps end-to-end: as far as we know the fastest performance for a WAN optimization system.

In this paper, we introduce an FPGA-accelerated partial image retrieval engine, suitable for a visualized document search system. To achieve efficient sharing and reuse of digitized documents, this system has the function of partial duplicate image retrieval. To meet the demand for stability and speed, we introduced a brute-force matching of the BRIEF descriptor with two step scheme and an FPGA accelerator with a thoroughly parallelized and pipelined architecture to educe the potential of the FPGA. The FPGA accelerator significantly improves the runtime performance of the engine. It is about 65 times better than a CPU-based solution on average. Ultimately, we developed a prototype document search system, and the proposed engine contributes to the intuitive retrieval and quick response of the system.

This paper focuses on an estimation problem of model parameters in software reliability modeling. We introduce the EM (expectation-maximization) algorithms for software reliability models and compare them with the classical parameter estimation methods. Especially, we extensively develop the EM algorithms for two cases; (i) the time interval data of software fault detection are available, (ii) additive software reliability models based on non-homogeneous Poisson processes are used. In numerical examples, we compare the iterative schemes based on the EM algorithms with classical methods such as the Newton's method and the Fisher's scoring method and show that the EM algorithms are attractive in terms of convergence property.