We reported a high-frequency piezoelectric resonator (PZR)-based cascaded fractional-N PLL featuring channel adjusting technique with sub-ppb-order frequency resolution, which can overcome the difficulty using the narrow range GHz PZR. This paper details a design of the proposed cascaded PLL. In order to reduce power consumption of 2nd-PLL, a power-efficient latch for pre-scaler is proposed. 3rd-1st cascaded delta-sigma-modulator can reduce the number of gates. The prototype PLL was fabricated in a 65nm CMOS and achieved 8.484GHz to 8.912GHz output, 180 fs rms-jitter, and −244 dB FOM while consuming 12.7mW.

This paper presents design of the low power RF transceiver [1] which is suitable for wireless sensor network. Using 5.8GHz band has potentiality to achieve small size wireless sensor module because of smaller antenna in higher frequency. The proposed transceiver utilizes different modulation schemes for uplink and downlink to optimize power consumption and spectral efficiency. In addition, supply voltage of 0.5V can reduce the power consumption of overall RF transceiver. The prototype transceiver was fabricated in 65nm CMOS process, and the transmitter achieved EVM of 12.6% while consuming 2.86mW, and the receiver realizes sensitivity of -75dBm while consuming 0.83mW.

This paper presents a low-power RF-CMOS-transceiver IC-module with small antennas on a printed circuit board (PCB). Active mixer-first architecture is employed on a receiver for achieving both acceptable sensitivity and lower power. We also show strategies for lowering power consumption of the transmitter and the phase locked loop (PLL): a high-gain inverter-based resonant-driver and a current-reuse voltage controlled oscillator (VCO). Power saving of the RF circuits is achieved with low supply-voltage design under 0.5V by exploiting forward body bias technique. The use of 5.5-GHz band and a J-shaped folded monopole antennas (JFMA) on the PCB enable to reduce the module footprint, and the module size of 0.78 cc is realized. The proposed transceiver circuit is fabricated in 65 nm CMOS process technology and is mounted on the PCB. 5.5-GHz RF-transceiver operation is succeeded with small power consumption of 1.56 mW under 0.5-V power supply. Output signal-power of the transmitter is −23.2 dBm, and receiver sensitivity is −61.2 dBm.

This paper proposes an ultra-low-power 5.5-GHz PLL which employs a divide-by-4 injection-locked frequency divider (ILFD), which is calibrated by digital circuits, and linearity-compensated varactors for low supply-voltage operation. The proposed PLL was fabricated in 65nm CMOS. It shows a 1-MHz-offset phase noise of -106 dBc/Hz and the total power consumption of 950μW at 5.5 GHz.

This paper proposes an ultra low power pH-monitoring IC featuring a wireless FM-transmitter with duty cycling operation and the use of an Ion Sensitive Field Effect Transistor (ISFET) for dentistry application. The IC achieves wireless communication and pH sensing under very low current consumption thanks to duty cycling operation and heavily stacked-transistor design. 0.18 μm CMOS process technology is used to fabricate a prototype chip, and current consumption of 2.0 μA was measured.

In this paper, we propose a process-variability-aware adaptive test flow that realizes efficient and comprehensive detection of parametric faults. A parametric fault is essentially a malfunction in a large-scale integration chip, which is caused by the variability in fabrication processes. In our adaptive test framework, test pattern sets are altered on individual chips in order to apply the optimal set of test patterns for each chip, and thus the test coverage is improved and the test time is reduced. The test pattern is chosen on the basis of parameter estimations measured using an on-chip sensor with respect to statistical timing information. We also propose a novel metric to quantize the test coverage suitable for evaluating the test quality of parametric faults. Our experimental results using an industrial design show that the proposed flow significantly improves the parametric fault coverage and test efficiency compared to conventional test flows.

We introduce “Wafer Shuttle” that is suitable for integration of diverse functionalities. CMOS/MEMS design flow and environment based on SPICE is discussed. It is pointed out that modeling will be important to promote the R&D of MEMS/CMOS and/or diverse-functionalities integration on CMOS.

A predictable device models should correctly handle parameter variations. Good recognition of the variation of physical parameters, which are being the sources of current variations of modern devices, is thus significantly important. In this paper, we present a practical procedure for decomposing device current variation into physical parameter variations. Based on the I-V curve measurements, two variation components: threshold voltage variation and gain-factor variation are clearly separated. Cause of gain-factor variation is further discussed with measurement results of poly-Si resistor. The impact of the variation-sources on circuit performance is also evaluated using SRAM noise margin as an example.

A novel technique that estimates on-chip process parameters, such as threshold voltages or channel length, is proposed. The proposed method is particularly useful as process condition estimator for reliability and yield enhancement techniques such as adaptive delay test or post-fabric performance compensation. Test paths consisting of a flip-flop and designated delay circuit, which is sensitive to individual process parameters, are inserted to obtain simultaneous delay inequalities. Then, the inequalities are solved for process parameters. The test path insertion is only on short paths to reduce delay and area overhead. Through numerical experiments, the proposed estimation flow using 150 paths achieve 10mV accuracy in estimating threshold voltages.

Adaptive test is one of the most efficient techniques that practically ensure high yield and reliability of designed chips. In this paper, a novel path-clustering method suitable for the adaptive test, in which test paths are altered according to the monitored process-parameters, is proposed. Considering the probability function of the die-to-die systematic process variation, the proposed method clusters path sets so that the total number of test-paths are minimized. For quantitative evaluation of different clusterings, figure of merit for clustering, which represents the expected number of test-paths at a particular test coverage, is also proposed. The proposed clustering is experimentally evaluated by applying to an industrial circuit. With our clustering, the average test paths in the adaptive test have been reduced to less than 50% compared with the ones of the conventional test.

The continuing miniaturization of LSI dimension is causing the increase of process-related variations which significantly affects not only its design turn around time but also its manufacturing yield. Statistical static timing analysis (SSTA) is expected as a promising way to estimate the performance of circuits more accurately considering delay variations. However, LSIs designed using SSTA may have higher probability of parametric faults than the ones designed with deterministic timing analysis. In order to test these parametric faults, effective extraction techniques of critical paths are needed. In this paper, we discuss a general trend between the delay margin of LSIs designed by SSTA and their parametric fault ratio. Then we propose an adaptive test flow for parametric faults using statistical static timing information, and a concept of parametric fault coverage. Experimental results demonstrate the effectiveness of our approach.

This paper demonstrates a low voltage differential signaling (LVDS)-type on-chip transmission line (TL) interconnect to solve delay issues on global interconnects. The proposed on-chip TL interconnect can achieve 10.5 Gbps signaling and has smaller delay, smaller delay variation and better power efficiency than conventional on-chip interconnects at high-frequencies.

This paper presents a novel small-area distributed mixer for ultrawide-band (UWB) receivers. The proposed mixer uses five 4-port inductors instead of fifteen 2-port inductors to shrink area of the circuit. The proposed mixer achieves conversion gain of -10 dB, noise figure of 15 dB, return loss of less than -10 dB from 2.3 to 6.0 GHz, IIP3 of 13.6 dBm, and the circuit area of 0.51 mm2.

A procedure that decomposes measured parametric device variation into systematic and random components is studied by considering the decomposition process as selecting the most suitable model for describing on-die spatial variation trend. In order to maximize model predictability, the log-likelihood estimate called corrected Akaike information criterion is adopted. Depending on on-die contours of underlying systematic variation, necessary and sufficient complexity of the systematic regression model is objectively and adaptively determined. The proposed procedure is applied to 90-nm threshold voltage data and found the low order polynomials describe systematic variation very well. Designing cost-effective variation monitoring circuits as well as appropriate model determination of on-die variation are hence facilitated.

We present a new statistical STA framework based on Monte Carlo analysis that can deal with arbitrary statistical distribution and delay models. Order statistics (non-parametrics) is consistently adopted by which the timing analysis and criticality calculation become distribution-independent. To make Monte Carlo process computationally practical, delays are handled as vectors so that iterations are eliminated. The vector dimension or required number of Monte Carlo iterations which guarantees no timing violation at any user-specified probability is analytically determined. A path criticality metric using order statistics is also defined. Experimental results using various delay models show the validity and usefulness of our proposed algorithm.

This paper proposes a self compensation technique. For LNAs, large power gain and large input signal results in too large output signal and distortion. To make matters worse, input power varies by process variation, temperature, simulation error, and so on. To solve the problem, the proposed LNA is equipped with variable bias circuit and can be reconfigured by bias voltage of transistors. It contributes to power reduction, compensation of intermodulation. The proposed LNA achieves more than 33 dBm in DeltaIM3, if the input power increases more than -30 dBm. Moreover the output power is less than about -12 dBm, which is 87 % of power reduction.

This paper proposes a wide-range tunable CMOS voltage controlled oscillator (VCO). VCO uses an on-chip variable inductor and switched capacitors as variable elements. The VCO was fabricated using a standard 0.18 mum CMOS process with five metal layers. The oscillation frequency can be tuned from 1.28 GHz to 2.75 GHz with tuning range of 72 %.

This paper proposes a branching method for on-chip transmission line (TL) interconnects, which can reduce delay and power of global interconnects. A 6-mm-long TL interconnect with a branch is fabricated by using a 0.18 mum standard Si CMOS process, and the measurement result performs 4Gbps signal transmission.

Stochastic approaches for effective power supply network optimization are proposed. Considering node voltages obtained using dynamic voltage drop analysis as sample variables, multi-variate regression is conducted to optimize clock timing metrics, such as clock skew or jitter. Aggregate correlation coefficient (ACC) which quantifies the resistivity between different chip regions is defined in order to find apossible insufficiency in the wire connections of the powersupply network. Based on the ACC, we also propose a procedure using linear regression to find the most effective region for improving clock timing metrics. In our example, clockskew has been reduced by 20% through two iterations.

This paper proposes a reconfigurable low noise amplifier (LNA). The proposed LNA equips variable bias circuit and can be reconfigured by bias voltage of transistors. It contributes to power reduction, compensation of intermodulation, and output signal to noise ratio (SNR/sub out/). The proposed LNA achieves 73 % of power reduction by controlling bias voltage, and dynamic compensation of /spl Delta/IM3 and SNR/sub out/ is realized.

On-chip transmission-line interconnect has been proposed to reduce delay time and power consumption. The transmission line is used to replace long RC interconnects. This paper proposes the methodology to replace RC lines with transmission lines, which are estimated with Wire Length Distribution (WLD). Advantages of on-chip transmission line are discussed from the view point of delay time and power consumption.

This paper proposes a dynamic reconfigurable architecture for analog RF circuits. The architecture consists of RF circuits and a control circuit. The RF circuits can be reconfigured by bias voltages of transistors and variable passive components, and the RF circuit block can also be switched dynamically. The proposed architecture can realize the multi-band/mode RF circuit in single chip for the Software Defined Radio, which achieves considerable reduction of circuit area and power consumption. On the other hand, we can obtain robust RF circuits by the dynamic reconfiguration for the process variation, the dynamic change of temperature, etc.

Interconnect length distribution (ILD) represents a correlation between the number of interconnects and length. The ILD can predict power consumption, clock frequency, chip size, etc. It has been said that high core utilization and small circuit area improve chip performance. We propose a ILD model to predict a correlation between core utilization and chip performance. The proposed model predicts influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decrease of load capacitance is more important than that of total interconnect length for improvement of chip performance. The proposed ILD model expresses actual ILD more accurate than conventional models.

We have proposed an intracell reverse link of an SS-CDMA flexible wireless network based on an approximately synchronized (AS) CDMA. The AS-CDMA features no co-channel interference during a guard-chip duration. A sequence with the guard-chip duration can be designed using the pseudo periodic method and the orthogonal frequency multi-channel method. The reverse link without co-channel interference does not require the sophisticated transmission power control, which is indispensable in the conventional systems such as IS-95. The AS-CDMA modem has been designed and implemented for the Japanese 2.4 GHz SS band. An AS-CDMA sequence of length 48 is designed. The number of the orthogonal frequency multi-channel method is 2. One of the features of the implemented reverse link modem is the use of a surface-acoustic-wave convolver as a correlator for rapid synchronization. The effects of frequency offset on stability have been evaluated using computer simulation. The simulation results have shown that the degradation of E/sub b//N/sub o/ at a BER of 10/sup -4/ is 1.4 dB, when the carrier frequency offset of an undesired signal is /spl plusmn/1 ppm and the desired-undesired signal power ratio is -30 dB. In the implemented AS-CDMA reverse link modem, the measured degradation of E/sub b//N/sub 0/ has been found to be 3.0 dB at a BER of 10/sup -4/.

We have implemented a switched current matched filter (SIMF) LSI for the synchronization channel of IMT-2000. A partial correlation structure has been proposed for reducing current transfer error accumulation, which degrades correlation dynamic range. Degradation of the correlation dynamic range can be improved 1.8 dB at the current transfer error of 1%. Power consumption of 7.5 mW has been estimated with 93% current-cut. 64 chip SIMF has been fabricated using 0.8 /spl mu/m CMOS process. The correlation peaks can be clearly observed at the chip rate of 4 Mcps. 0.2-dB degradation of probability of synchronization error has been obtained.

A new compact 2.4 GHz spread spectrum (SS) modem has been implemented using a surface acoustic wave (SAW) correlator. The authors have designed and fabricated the 2.4 GHz SAW correlator on AlN/Al/sub 2/O/sub 3/ combination. Using the SAW correlator and SAW delay line at the RF front-end, the 2.4 GHz SS signal is directly demodulated to baseband data. The PN code used is the 11-chip Barker code whose rate is 22 MHz, and baseband data rate is 2 Mbps. The degradation of the measured BER from the theoretical limit is found to be less than 3 dB of E/sub b//N/sub 0/. The authors propose a time division multiplex scheme utilizing the orthogonality of the spreading PN code in the time domain. The channel multiplex is experimentally confirmed using shifted Barker codes.