Unsupervised Chinese word segmentation (UCWS) has made progress by incorporating linguistic knowledge from pre-trained language models using parameter-free probing techniques.However, such approaches suffer from increased training time due to the need for multiple inferences using a pre-trained language model to perform word segmentation.This work introduces a novel way to enhance UCWS performance while maintaining training efficiency.Our proposed method integrates the segmentation signal from the unsupervised segmental language model to the pre-trained BERT classifier under a pseudo-labeling framework.Experimental results demonstrate that our approach achieves state-of-the-art performance on the seven out of eight UCWS tasks while considerably reducing the training time compared to previous approaches.

In deep submicron process, parametric yield loss due to process variations has become a critical issue, especially for sensitive analog circuits. Design centering is one of the popular techniques to find the nominal design that leads to the maximum yield. However, in critical cases, it is possible that some parts of the performance distribution are still outside the feasible region and has no way to further improve the yield. Therefore, a process sensitivity reduction flow for analog circuits is proposed in this paper. Without moving the given nominal point, a new set of device sizes that lead to smaller performance distribution range can be obtained in the proposed sizing flow, which helps to further improve the yield of that design.