A 14-bit 500-MS/s synthesizable current-steering digital-to-analog converter (CS-DAC) is presented by using the digital place-and-route (DPR) tools. The proposed unit current cells for the CS-DAC are presented to relax the issues due to the auto-routed wires by using DPR tools and the layout-dependent effects (LDEs). For the unit current cells, the clustered placement method is used to improve the timing skews induced by the auto-routed wires. To reduce the parasitic coupling capacitances, the bias rail is presented for the unit current cells. A plug-in layout method is used to meet the current density requirement and reduce the parasitic capacitances due to the limited width of the auto-routed wires. By using the DPR tools, the layout time is significantly reduced compared with the manual layout. This 14-bit 500-MS/s CS-DAC is fabricated in 40-nm CMOS technology. It consumes 12.42 mW from a 1.1-V supply at a rate of 500 MS/s. At the temperature of 300 K, it achieves >50-dBc spurious-free dynamic range (SFDR) and$\lt -66$-dBc third-order intermodulation distortion (IM3). At the temperature of 4 K, it achieves >43 dBc SFDR and$\lt -66$dBc IM3.

This paper presents a 36 Gb/s (23.04 GBaud) 3-level pulse amplitude modulation (PAM-3) receiver (RX). The proposed inductor-reused continuous-time linear equalizer (CTLE) uses feedforward and inductive peaking techniques. Additionally, the number of the data slicers is reduced in the PAM-3 receiver with a loop-unrolled decision feedback equalizer (DFE). Furthermore, a baud-rate phase detector (BRPD) is presented. Fabricated in 22-nm CMOS technology, this receiver compensates for a channel loss of 20.5 dB at 11.52 GHz, achieving a bit error rate (BER) of less than$10^{-12} $with a pseudo-random ternary sequence (PRTS) of$3^{7}\mathbf {-}1$. The measured clock integrated jitter is 267 fsrms at 720 MHz, and the retimed data exhibits 10.98 pspp jitter. The overall receiver consumes 51.7 mW, with a calculated energy efficiency of 1.44 pJ/b and a figure of merit (FoM) of 0.07 pJ/b/dB.

This article presents a 40-Gb/s (25.6-GBaud) three-level pulse amplitude modulation (PAM-3) baud-rate receiver with one-tap decision-feedback equalize (DFE). A baud-rate phase detector (BRPD) that locks at the point with zero first postcursor is proposed. In addition, by reusing the BRPD’s error samplers, a weighting coefficient calibration is presented to select the DFE weighting coefficient that maximizes the top level of the eye diagram, thereby improving eye height across different channel losses. An inductorless continuous-time linear equalizer (CTLE) and a variable gain amplifier (VGA) are also included. The VGA adjusts the output common-mode resistance to control data swing, reducing power consumption when the required swing is small. Furthermore, by using the modified summer-merged slicers, the capacitance from the slicers to the VGA is reduced. Finally, a digital clock/data recovery (CDR) circuit is presented, which includes a demultiplexer (DeMUX) with a short delay time to reduce the loop latency. The 40-Gb/s PAM-3 receiver is fabricated in 28-nm CMOS technology. For a 25.6-Gbaud pseudorandom ternary sequence of$3^{7}$–1, the measured bit error rate (BER) is below$10^{-12}$for channel losses of 9 and 17.5 dB. At a 9-dB loss, total power consumption is 35-mW with a calculated FoM of 0.875-pJ/bit. At 17.5-dB loss, total power consumption is 38-mW with a calculated FoM of 0.95-pJ/bit.

A 16-Gb/s baud-rate clock and data recovery (CDR) circuit with a one-tap decision-feedback equalizer (DFE) and a wide frequency capture range (FCR) is presented. The proposed asymmetrical pattern-based phase detectors are used to achieve a wide FCR. This quarter-rate CDR circuit is fabricated in 40-nm CMOS technology and the active area is 0.1094 mm2. For a 16 Gb/s PRBS of 27–1, the power of the CDR circuit is 38.4 mW and its calculated energy efficiency is 2.4 pJ/b. The measured FCR is 40.6%.

A 32-Gb/s$2\times $half-baud-rate (THBR) clock and data recovery (CDR) circuit is presented by using a phase detector (PD) and a frequency detector (FD). The frequency detection range of the FD is analyzed. This prototype is fabricated in a 28-nm CMOS process with an active area of 0.055 mm2. The measured frequency capture range is 43.7% for a 32-Gb/s pseudorandom bit sequence (PRBS) of 27-1. This proposed CDR circuit achieves a bit error rate of less than$10^{-12}$under the channel loss of 23 dB at 16 GHz. The total power consumption is 58.6 mW at 32 Gb/s and achieves a figure-of-merit (FoM) of 0.079 pJ/bit/dB.

A 36-Gb/s 2$\times$half-baud-rate (THBR) adaptive receiver (RX) is presented. The pattern-based adaptation method for adjusting the frequency response of a continuous-time linear equalizer (CTLE) is proposed. In addition, the reference voltage of the comparators is adapted to enhance the timing margin of the recovered clock in the RX. This THBR adaptive RX is fabricated in TSMC 28-nm CMOS technology with a core area of 0.097 mm$^{2}$. The measured bit error rate (BER) is less than 10$^{-12}$for a 36-Gb/s pseudorandom binary sequence (PRBS) of 2$^{7}$$-$1, when the channel loss is 19 dB at 18 GHz. The total power consumption of this RX is 76 mW with gated adaptation circuits. The calculated figure of merit (FoM) is 2.1 pJ/bit.

This article presents a 40-Gb/s (25.6 GBaud) quarter-rate receiver utilizing three-level pulse amplitude modulation (PAM). The continuous-time linear equalizer (CTLE) with a passive high-pass filter provides a boosting gain of 13 dB at 12.8 GHz. A two-tap data decision feedback equalizer (DFE) and a one-tap edge DFE are included. The phase detector (PD) logic directly controls the digitally controlled oscillator (DCO) to reduce the loop latency. This receiver is fabricated by a 28-nm CMOS process and its area is 0.12 mm$^{2}$. By using a pseudorandom ternary sequence (PRTS) of 3$^{7} - 1$, this 40-Gb/s receiver compensates the channel loss up to 23-dB loss with a bit error rate (BER)$<$10$^{-12}$. The total power consumption of this receiver is 90 mW at 40-Gb/s, which achieves an FoM of 98 fJ/bit/dB.

A 12.93–16 Gb/s reference-less and baud-rate clock and data recovery (CDR) circuit with a one-tap speculative decision-feedback equalizer (DFE) is presented. By using the semirotational frequency detection (SRFD), a baud-rate frequency detector (FD) is presented. This FD reuses hardware of the pattern-based phase detector and the one-tap DFE. This CDR circuit is fabricated in 40-nm CMOS technology and its active area is 0.117 mm2. The total power is 40.6 mW and the calculated power efficiency is 2.54 pJ/b at 16 Gb/s.

A 12-bit 20-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is presented by using the digital place-and-route (DPR) tools. The macrocells for the capacitive digital-to-analog converter, the bootstrapped switch, and the dynamic comparator are presented. The custom standard cells for the dynamic SAR logic are also presented. By using the macrocells and the custom standard ones, the layout of this SAR ADC is completed by using the DPR tools. Several techniques are presented to improve the parasitic capacitances, the current density of the metal interconnections, and the nonideal effects caused by the DPR tools. This SAR ADC is fabricated in 40-nm CMOS technology and its active area is 0.0067 mm2. To compare with the full-custom method, the proposed DPR flow has speeded up by a factor of 288 to complete the interconnection wires. Its power dissipation is 363$\mu \text{W}$at 20 MS/s and the calculated Walden FoM is 23 fJ/c. step at Nyquist frequency.

A 10.4-16-Gb/s reference-less and baud-rate clock and data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE) is presented. The quarter-rate CDR circuit uses a pattern-based phase detector (PD) and the proposed FD. This wide-range FD is composed of a coarse FD and a fine FD (FFD) which share the same front-end comparators with the PD and the DFE. Thus, no extra comparators are required. In addition, by monitoring the drift direction of five samples on the five-bit data patterns, the FFD performs an error-free operation within a frequency error of 7.7%. Therefore, the CDR has a robust FD-to-PD transition. By using the proposed FD, this CDR circuit not only achieves a wide frequency capture range of 43%, but also has a short frequency settling time of$680~\mu \text{s}$. This CDR circuit is fabricated in 40-nm CMOS technology and occupies an active area of 0.1004 mm2. The total power of the receiver is 39.9mW at 16 Gb/s, and the calculated energy efficiency is 2.49pJ/b.

A 2.4-GHz area-efficient and fast-locking subharmonically injection-locked type-I phase-locked loop (SIL-TPLL) is presented. A timing-adjusted phase detector (TPD) is proposed to calibrate the injection timing. This TPD also reduces the settling time of the SIL-TPLL. The loop capacitance of the type-I PLL is tiny to save the area. This SIL-TPLL is fabricated in 45-nm CMOS technology. Its active area is 0.013 mm2. The power consumption is 5.6 mW at 2.4 GHz for a supply of 0.87 V. The integrated jitter of the SIL-TPLL over 1 kHz to 40 MHz is 0.91 ps.

We present a 64-Gb/s four-level pulse amplitude modulation (PAM-4) optical receiver with the amplitude/phase correction and the threshold voltage/data level calibration, utilizing an inverter-based transimpedance amplifier (TIA). A variable gain amplifier (VGA) with the amplitude/phase correction is also presented. The threshold voltage of the data slicers and the data levels for the error slicers are calibrated. A three-tap decision feedback equalizer is utilized to compensate for the intersymbol interference. The tap coefficients are calibrated by using the sign-sign least-mean-square algorithm. This PAM-4 optical receiver is fabricated in a 40-nm CMOS process. For the TIA with five VGAs, the measured maximum amplitude imbalance is less than 0.4 dB and the phase imbalance is less than ±1°. Its power is 420 mW from a supply of 1.1 V excluding the output buffers. Its core area is 2.2 mm2.

In this brief, a relaxation oscillator with comparator delay compensation is presented. Two digital compensation loops are introduced to compensate for the comparator delay. This relaxation oscillator is fabricated in the 0.18-μm CMOS process. The measured average oscillation frequency is 943.1 kHz. The whole oscillator consumes 5.2 μW under a 0.9-V supply. The measured average temperature coefficients (TCs) of the oscillation frequency with and without compensation are 93.88 and 618.17 ppm/°C, respectively. It achieves a TC improvement of 6.6×. The measured frequency variation is within ±0.7% from -10 °C to 100 °C by using the DCLs. The measured line sensitivity is 4.37%/V. The measured figure of merit (FOM2) is 173.3 dB.

A low-phase-noise relaxation oscillator uses a digital compensation loop to reduce its temperature coefficient (TC). This relaxation oscillator is fabricated in the 0.18-μm CMOS process. The measured average oscillation frequency is 13.4 MHz. The whole oscillator consumes 157.8 μW under a 1.2-V supply. The measured average TCs of the oscillation frequency with and without compensation are 193.15 and 1098.7 ppm/°C, respectively. The TC achieves an improvement of 5.7 times. The measured frequency variation is within ±2% from -20 °C to 100 °C by using the digital compensation loop. The measured phase noise at 100-kHz offset frequency is -104.82 dBc/Hz, and the measured figure of merit (FOM) is -154.4 dBc/Hz.

In this brief, a multiplying delay-locked loop (MDLL) using a frequency calibrator (FC) and a voltage monitor (VM) is presented. This FC uses a delay-calibrated subsampling phase detector (SSPD) to reduce the frequency error. The VM is used to cover a wide frequency variation. This MDLL is fabricated in 40-nm CMOS technology. Its active area is 0.013 mm2, and the power consumption is 5.2 mW from a supply of 1 V. It exhibits a root-mean-square jitter of 229 fs at 2.4-GHz output and the reference spur of -54.3 dBc under a reference clock of 150 MHz.

A frequency-drift-compensated phase-locked loop (PLL) with an LC voltage-controlled oscillator (VCO) is fabricated in TSMC 40-nm CMOS process. The proposed frequency drift compensator employs an analog-to-digital converter to monitor the control voltage of the PLL in background. The capacitor banks are adjusted to compensate for the frequency drift of the LC-VCO. The measured reference spur is -65.15 dBc. The measured best phase noise of this PLL is -108.32 and -130.26 dBc/Hz at the frequency offset of 1 and 10 MHz, respectively, among five chips. This chip occupies 0.223-mm2active area. The power dissipation of this PLL is 6.32 mW from a 0.9-V supply voltage. The average temperature coefficient is 2.43 ppm/°C from 20 °C to 100 °C.

Two two-step cyclic time-domain analog-to-digital converters (TADCs) in a 0.18-μm CMOS process are presented. The proposed TADC uses a voltage-to-time converter (VTC) with a 12-dB gain amplifier, and a time amplifier to achieve a 12-bit resolution. Only linear gain calibration is needed for the TADC. The first TADC achieves a spurious-free dynamic range (SFDR) of 70.5-dB and a signal-to-noise-plus distortion ratio (SNDR) of 64.3 dB. Its power consumption and area are 3 mW and 0.61 mm2, respectively. The noise analysis for each TADC building block is presented. The calculated results are verified by the transient noise analysis tool in HSPICE. To verify the noise analysis further, a second TADC is fabricated using the VTC with the device size scaled down by a factor of 4 based on the noise analysis. The second TADC achieves an SFDR of 66.8 dB and an SNDR of 59.1 dB. Its power consumption and area are 2.9 mW and 0.61 mm2, respectively.

The variability and leakage current in nanoscale CMOS technology may degrade the circuit performances significantly. To accommodate the above issues in a wide-range phase-locked loop (PLL), a self-healing prescaler, a self-healing voltage-controlled oscillator (VCO), and a calibrated charge pump (CP) are presented. This PLL is fabricated in a 65-nm CMOS technology and its active area is 0.0182 mm$^{2}$. For the self-healing VCO, its measured frequency range is from 60 to 1489 MHz. When this PLL operates at 855 MHz, the measured rms and peak-to-peak jitters are 8.03 and 55.6 ps, respectively. The measured reference spur is -52.89 dBc. This PLL consumes 4.3 mW from 1.2 V supply without buffers.

The design and implementation of a high-speed voltage-controlled oscillator (VCO) in 65-nm CMOS technology is presented. The proposed VCO oscillates at the secondary resonant pole of itsLCresonator and achieves a frequency enhancement of 84.7% while compared with a conventional cross-coupled VCO. The proposed VCO is also incorporated into a phase-locked loop (PLL) to generate clock signals above 100 GHz. For a 1.2-V supply, the measured tuning range of this VCO is from 103.057 to 104.581 GHz, and the measured phase noise of this VCO is -101.08 dBc/Hz at 10-MHz offset. The locking range of the PLL is from 103.058 to 104.58 GHz, and its measured in-band phase noise is -80.41 dBc/Hz at 1-MHz offset. The measured reference spur level of this PLL is less than -63.8 dBc while consuming 63 mW from a 1.2-V supply.

A digitally-calibrated technique to suppress the supply voltage sensitivity of a phase-locked loop (PLL) is presented. The voltage-controlled ring oscillator with an additional opposite-supply-sensitivity pair is digitally calibrated to suppress the supply voltage sensitivity. The circuit is fabricated in a 0.18-m CMOS technology and the core area occupies 0.235 mm2. The total power consumption is 16.2 mW for a supply voltage of 1.8 V and an operating frequency of 1.5 GHz. For a 100 mVpp, 110 kHz sinusoidal waveform noise applied to the supply, the measured rms jitters without and with calibration are 16.5 and 9.7 ps, respectively, while this PLL works at 1.5 GHz. This PLL achieves the rms jitter improvement by a factor of 41.2% under the proposed digitally-calibrated technique.

A 140 MS/s 10-bit pipelined analog-to-digital converter (ADC) using a folded sample-and-hold (S/H) stage and a 5-bit flash ADC is presented. To conquer the limited linear swing range results from an operational amplifier (OP-AMP). The proposed folded S/H stage allows the ADC to operate in the linear swing range of an OP-AMP. Only 17 comparators are required for a 5-bit flash ADC. Corresponding digital correction codes are added. The single-phase triggering method is adopted and it saves half the number of shift/latch elements. This pipelined ADC has been fabricated in a 0.18 um CMOS process. It dissipates 65 mW for a supply voltage of 1.8 V. The measured signal-to-noise-plus-distortion ratio (SNDR) is achieved 55.4 dB. The differential nonlinearity (DNL) and integral nonlinearity (INL) is 0.78-LSB and 0.98-LSB, respectively.