When designing an SoC (system-on-chip), one should ensure that the chip's architecture delivers optimal data throughput for high-speed connectivity blocks on practical use, taking of several layers of software into account. Previous works such as simulation based estimation method or analytical method that focused on estimation of low level throughput in link layer are not adequate for accurately estimating throughput of the real silicon SoC because practical use cases of such complex connectivity blocks typically require extensive software operation on top of platform operating systems like Linux. FPGA-based emulation, therefore, is commonly used to verify functional correctness of complex connectivity blocks in a more realistic usage scenario with real connectivity devices like USB 2.0 mass storage devices. Speed of FPGA emulation, though, is scaled down significantly because of inherent limitation of FPGA emulation while speed of interface to real connectivity devices is required to be at-speed for compliance with connectivity specification standards. For this reason, scaling factors of speed are not uniform and, thus, measurement of performance is not accurate. This paper proposes a method to compensate errors due to the non-uniform scaling factors. In the proposed method, measurements of various parameters in FPGA emulation are applied to a high-accuracy estimation model that we created. Our method was applied to USB2.0, and the experimental result shows 4.1% of estimation error.