Understanding the relationship between coverage and test-templates (a generic term we use to describe the inputs for the random stimuli generator) is an important layer in understanding the state and progress of the verification process. Today, this is extremely hard to achieve and is based on expert knowledge. Template Aware Coverage (TAC) is a novel approach to meeting this challenge. Based on collecting statistics of the relations between coverage and test-templates, TAC maintains these statistics in efficient data structures. It also introduces analytics means to provide useful information based on this data. Template Aware Coverage is currently being used in the verification of a high-end processor systems, where it significantly helps hitting hard-to-hit coverage events as well as never hit events.

This paper addresses the challenges of minimizing the time and resources required to validate the changes between two Hardware (HW) model iterations of the same design. It introduces CLTV (Coverage Learned Targeted Validation), an automatic framework which learns during the verification process of the HW and uses the learned information to target the areas of the design that are affected by the incremental HW model iterations.

We report on our experience with a new test generation language for processor verification. The verification of two superscalar multiprocessors is described and we show the ease of expressing complex verification tasks. The cost and benefit are demonstrated: training takes up to six months; the simulation time required for a desired level of coverage has decreased by a factor of twenty; the number of escape bugs has been reduced.