An approach to simultaneous placement and routing of hierarchical IC layouts is presented. The method is based on the concept of slicing, which introduces a specific regularity to the problem at certain constraints on the chip floorplan. The placement part consists of a number of interrelated linear ordering problems, corresponding to the ordering of slices. The routing part outlines a hierarchical pattern router, applicable to slicing structures. The IC layout construction progresses top-down in small design increments, corresponding to processing of the individual slices. The placement and routing data are acquired at intervening time slots and influence each other on each hierarchy level.

The paper presents an IC-layout assembler which is capable of transforming the structural description of a system into general chip layout expressed in CIF. The chip assembly is based on the efferent decision flow. The process is one of gradual refinement of the starting domain yielding successively lower level chip components down to the primitives.

The concept of the genealogical approach to the layout problem is presented. The system pursues the idea of flexible modules and is capable of dealing with arbitrarily complex tasks.