Modern engineering, spanning electrical, mechanical, aerospace, civil, and computer disciplines, stands as a cornerstone of human civilization and the foundation of our society. However, engineering design poses a fundamentally different challenge for large language models (LLMs) compared with traditional textbook-style problem solving or factual question answering. Although existing benchmarks have driven progress in areas such as language understanding, code synthesis, and scientific problem solving, real-world engineering design demands the synthesis of domain knowledge, navigation of complex trade-offs, and management of the tedious processes that consume much of practicing engineers' time. Despite these shared challenges across engineering disciplines, no benchmark currently captures the unique demands of engineering design work. In this work, we introduce EngDesign, an Engineering Design benchmark that evaluates LLMs' abilities to perform practical design tasks across nine engineering domains. Unlike existing benchmarks that focus on factual recall or question answering, EngDesign uniquely emphasizes LLMs' ability to synthesize domain knowledge, reason under constraints, and generate functional, objective-oriented engineering designs. Each task in EngDesign represents a real-world engineering design problem, accompanied by a detailed task description specifying design goals, constraints, and performance requirements. EngDesign pioneers a simulation-based evaluation paradigm that moves beyond textbook knowledge to assess genuine engineering design capabilities and shifts evaluation from static answer checking to dynamic, simulation-driven functional verification, marking a crucial step toward realizing the vision of engineering Artificial General Intelligence (AGI).

As the end of Moore’s law approaches, chiplet integration technology (or chiplet technology) has emerged to revolutionize future semiconductor chip design. Chiplet technology provides unique advantages over 3-D-stacking technology, including a more cost-efficient and thermal-friendly integration of heterogeneous technologies. Although chiplet technologies have already begun to be used by the latest commercial chips, they have not been explored for commodity dynamic random access memory (DRAM) design yet. Harnessing its advantages for DRAM for the first time, this article evaluates the feasibility of chiplet-based DRAM architecture, considering various physical and electrical constraints imposed by a standard chiplet interface [i.e., universal chiplet interconnect express (UCIe)]. We further explore the DIMM architectures that simplify module packaging and assembly, leading to reductions in total die size and overall costs. The comprehensive cross-level analysis (i.e., device, circuit, chip, and system levels) shows that chiplet-based DRAM reducest_RCD+t_CAS, latency-critical DRAM timing parameters, by$1.32\times $–$1.39\times $, at the same energy consumption. In addition, a$1.39\times $–$2.28\times $improvement int_RRDis obtained. The reduced DRAM timing parameters improve the overall system performance by up to 8.8%–24.7% (geomean 3.4%–8.4%) in real-life benchmarks. The chiplet-based heterogeneous integration achieves a$1.27\times $higher chip-level yield compared with the monolithic chip, along with up to 10% reduction in overall cost compared with traditional DIMMs at emerging process technologies.

Markov blanket feature selection, while theoretically optimal, is generally challenging to implement. This is due to the shortcomings of existing approaches to conditional independence (CI) testing, which tend to struggle either with the curse of dimensionality or computational complexity. We propose a novel two-step approach which facilitates Markov blanket feature selection in high dimensions. First, neural networks are used to map features to low-dimensional representations. In the second step, CI testing is performed by applying the $k$-NN conditional mutual information estimator to the learned feature maps. The mappings are designed to ensure that mapped samples both preserve information and share similar information about the target variable if and only if they are close in Euclidean distance. We show that these properties boost the performance of the $k$-NN estimator in the second step. The performance of the proposed method is evaluated on both synthetic and real data.

Electrostatic discharge (ESD) has been shown to cause severe reliability hazards at the physical level, resulting in permanent and transient errors. We present the first analysis of the effects of ESD-induced errors on instruction-level computation. Our data were measured on a microcontroller test chip fabricated for this study, with discharges from a controlled ESD gun. cosmic-ray-induced soft errors have been widely researched, and modeled as single event upsets (SEUs). Our observations across multiple trials on 3 test chips show that in contrast to radiation-induced errors, ESD can cause much more widespread errors than SEUs. In our trials, we observed system hangs and clock glitches which are serious errors. We also observed errors in the following categories: multiple-bit corruptions across multiple registers, multiple-bit corruptions in the same register, and single-bit corruptions across multiple registers. At the instruction level, these errors manifest as system hangs or serious malfunctioning of I/O operations, interrupt operations, and data/program memory. We demonstrate that ESD-induced errors form a significant reliability threat to higher-level functionality, warranting modeling and mitigation techniques.

This paper presents a methodology to construct an equivalent circuit model of a packaged integrated circuit mounted on a field-induced charged device model electrostatic discharge tester. Circuit simulation is used to obtain the full-component current and voltage distributions. This paper focuses on predicting overvoltage stress at power domain crossing circuits.

A practical approach for the compact modeling of electrostatic discharge (ESD) protection devices, using the behavioral language Verilog-A, is presented. Models of the NMOS transistor, the vertical n-p-n transistor, the diode, and the resistor have been developed, suitable for circuit-level simulation. Large-signal and small-signal models are provided for transient and alternating current (ac) simulation, respectively. A self-heating model is included for accurate simulation of the device ON-resistance under transient high-current conditions.

This paper presents a methodology for the efficient modeling of substrate noise coupling. A closed-form Green's function for nonuniformly doped substrates is employed with the correct singular characteristics. A novel global surface impedance matrix scheme is introduced to efficiently model nonuniformly doped wells, channel stop implants, and buried layers. Layout, device, and netlist extractors are developed so as to integrate our boundary element method (BEM) solver with commercial layout and circuit simulation tools.

We present new macromodeling techniques for capturing the response of a CMOS logic gate to noise pulses at the input. Two approaches are presented. The first one is a robust mathematical model which enables the hierarchical generation of noise abstracts for circuits composed of the precharacterized cells. The second is a circuit equivalent model which generates accurate noise waveforms for arbitrarily shaped and timed multiple-input glitches, arbitrary loads, and external noise coupling.

Design guidelines for static and domino silicon-on-insulator (SOI) CMOS circuits are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-silicon. Most published design fixes for eliminating parasitic bipolar induced upset are shown to aggravate the charge sharing problem. A new and improved predischarge method for enhancing the noise tolerance of SOI domino circuits is thus proposed . The topic of multiple output domino logic in SOI technology is addressed for the first time. Multiple output domino logic is shown to be more prone to bipolar leakage induced upset than regular domino. Many of the design practices used to alleviate bipolar leakage in regular domino are no longer valid due to the multiple output domino logic's inherent design requirements. A novel SOI-specific multiple output domino logic, particularly suitable for adder designs, is introduced to minimize the bipolar leakage risk.

We present a comprehensive methodology for the electrodynamic modeling of substrate noise coupling. A new and efficient method is introduced for the calculation of the Green's function that can accommodate arbitrary substrate doping profiles and thus facilitate substrate noise analysis using boundary element methods. In addition to a discussion of the application of the method and its validation in the context of substrate transfer resistance extraction, preliminary results from its application to frequency-dependent substrate noise modeling are presented also.

We apply three-dimensional finite element analysis to study the thermal coupling between nearby interconnects. We find that the temperature rise in current-carrying lines is significantly influenced by a dense array of lines in a nearby metal level. In contrast, thermal coupling between just two neighboring parallel lines is insignificant for most geometries. Design rules for average root-mean-square current density are provided for specific geometries given the requirement that the interconnect temperature be no more than 5/spl deg/C above the substrate temperature. Semi-empirical formulae for coupling effects are presented based on the numerical results. A procedure is proposed to implement the formulae in computer-aided design tools.

Due to interactions through the common silicon substrate, the layout and placement of devices and substrate contacts can have significant impacts on a circuit's ESD (Electrostatic Discharge) and latchup behavior in CMOS technologies.Proper substrate modeling is thus required for circuit-level simulation to predict the circuit's ESD performance and latchup immunity.In this work we propose a new substrate resistance network model, and develop a novel substrate resistance extraction method that accurately calculates the distribution of injection current into the substrate during ESD or latchup events.With the proposed substrate model and resistance extraction, we can capture the three-dimensional layout par&tics in the circuit as well as the vertical substrate doping profile, and simulate these effects on circuit behavior at the circuit-level accurately.The usefulness of this work for layout optimization is demonstrated with an industrial circuit example.

We apply 3-D finite element analysis to study the thermal coupling between nearby interconnects.We find that the temperature rise in current-carrying lines is significantly influenced by a dense array of lines in the adjacent metal level.In contrast, thermal coupling between just two neighboring lines is insignificant for most geometries.Design rules for average current density are provided for specific geometries given the requirement that the interconnect temperature be no more than 5 "C above the substrate temperature.Semi-empirical formulae for coupling effects are presented based on the numerical results.

In this paper, we present a new chip-level electrothermal timing simulator for CMOS VLSI circuits. Given the chip layout, the packaging specification, and the periodic input signal pattern, it finds the on-chip steady-state temperature profile and the resulting circuit performance. A tester chip has been designed for verification of ILLIADS-T, and very good agreement between simulation and experiment was found. Using this electrothermal simulator, temperature-dependent reliability and timing problems of VLSI circuits can be accurately identified.

In this paper, we present a new electromigration reliability diagnosis tool (iTEM) for CMOS VLSI circuits. Unlike previous electromigration reliability tools, iTEM can estimate the interconnect temperature rise due to joule heating and heat conduction from the substrate using a newly developed lumped thermal model. By including the temperature effect, iTEM provides much more accurate electromigration reliability diagnosis. Moreover, it is computationally efficient, and can analyze circuit layouts containing tens of thousands of transistors on a desktop workstation.

In this paper, we present the first chip-level electrothermal simulator, iCET. For a given chip layout, packaging material, user-specified input signal patterns, and thermal boundary conditions, it automatically finds the CMOS on-chip steady-state temperature profile and the resulting circuit performance. iCET has been tested on several circuits and it can efficiently analyze layouts containing tens of thousands of transistors on a desktop workstation.

In this paper, we present a hierarchical reliability-driven CAD system for the design of electromigration resistant circuits.The top of the hierarchy aims at quickly identifying those critical interconnects with potential electromigration reliability problems.Then the detailed electromigration analysis of critical interconnects is carried out by an accurate and computationally ecient simulation tool (iTEM).This top-down approach provides a feasible solution to the complicated electromigration diagnosis problem.

Berkeley reliability tools (BERT) simulates the circuit degradation (drift) due to hot-electron degradation in MOSFETs and bipolar transistors and predicts circuit failure rates due to oxide breakdown and electromigration in CMOS, bipolar, and BiCMOS circuits. With the increasing importance of reliability in today's and future technology, a reliability simulator such as this is expected to serve as the engine of design-for-reliability in a building-in-reliability paradigm. BERT works in conjunction with a circuit simulator such as SPICE in order to simulate reliability for actual circuits, and, like SPICE, acts as an interactive tool for design. BERT is introduced and the current work being done is summarized. BERT is used to study the reliability of a BiCMOS inverter chain, and performance data are presented.>