This paper presents the APRIS Robot Challenge, a Collaborative Online Interdisciplinary and International Learning (COIIL) initiative focusing on quadcopter control to promote cross-disciplinary and global collaboration among students. By integrating students from diverse fields such as software, electrical, and mechanical engineering, the program aims to enhance international communication and problem-solving skills through practical, team-based projects. Utilizing design thinking and the Scrum framework, participants develop unique quadcopter applications, supported by model-driven development, simulation tools, and distributed development techniques to ensure effective remote collaboration. Our analysis covers the program's evolution over four years, outcomes, and insights into fostering international cooperation and technical expertise. This study underscores the significance of interdisciplinary education and the potential of virtual collaborative platforms to prepare students for global challenges.

The paper reports authors' experience in teaching software product lines (SPL) for senior engineers in the company. An effective way for education in the experience is to teach SPL as a paradigm consisting of some key ideas and show how we can introduce the paradigm into the development process. The authors have used PLUS as a reference of such development process. Feature modeling is taught not only as a means of variability modeling but also as a means to facilitate construction of abstraction hierarchy and separation of concerns. Giving anti-patterns of feature modeling and countermeasures to them helps engineers discuss construction of better feature models.

Bounded Model Checking (BMC) converts a verification problem within a user-specified bound into satisfiability checks of propositional formulas. As the bound deepens, the formulas become larger in size and harder to solve. In this paper, we propose a hybrid approach in which stateless explicit-state exploration (SESE) is integrated into the BMC process to improve the scalability and performance of BMC for the verification of properties expressed in Linear Temporal Logic (LTL). Specifically, SESE is utilized to traverse, under the constraints of Bounded-Context Switching (BCS), the state space of a system design and memorize legal execution paths. These paths are classified according to heuristic state predicates into path clusters, which are then encoded into propositional formulas representing, together with the encoded formula for an LTL property, independent BMC instances. Such BMC instances are solved with SMT solvers running on mutilcores in parallel. Once a counterexample is found for one of the instances, the entire model checking (SESE as well as BMC) terminates. This hybrid checking procedure progresses in an incremental fashion until either a counterexample is found or the user-specified bound is reached. We have implemented this proposed hybrid approach in a tool called Garakabu2 with Yices 2 as its back-end solver. The experimental results show that Garakabu2 outperforms significantly the state-of-the-art BMC methods implemented in SAL for both safety and liveness properties.

We propose a hybrid approach to improving the verification performance of SMT-based bounded model checking for LTL properties. In this approach, stateless explicit-state exploration is utilized to traverse, under the constraints of bounded context switches, the state space of a system design and memorize legal execution paths. These paths are classified according to certain predicates into path clusters, which are then encoded into propositional formulas representing, together with the encoded formula for an LTL property, independent BMC instances. Such BMC instances are solved with SMT solvers running on mutilcores in parallel. Once a counterexample is found for one of the instances, the entire model checking terminates. This hybrid checking procedure progresses in an incremental fashion until either a counterexample is found or the user-specified bound is reached. We have implemented this proposed hybrid approach in a tool called Garakabu2 with CVC4 as its backend solver. The experimental results show that Garakabu2 often outperforms the state-of-the-art pure BMC methods implemented in SAL infinite bounded model checker for both safety and liveness properties.

The Mining Software Repositories (MSR) field integrates and analyzes data stored in repositories such as source control and bug repositories to support practitioners. Given the abundance of repository data, scaling up MSR analyses has become a major challenge. Recently, researchers have experimented with conventional techniques like a supercomputer or cloud computing, but these are either too expensive or too hard to configure. This paper proposes to scale up MSR analysis using “general-purpose computing on graphics processing units” (GPGPU) on off-the-shelf video cards. In a representative MSR case study to measure co-change on version history of the Eclipse project, we find that the GPU approach is up to a factor of 43.9 faster than a CPU-only approach.

Reducing the energy consumed in the use of smart phones has become a major challenge for application developers. While this problem can be addressed at various levels, it is important to reduce the energy consumption of individual applications which can vary greatly depending on the behavior of the application. Energy profiling methods are required in order to identify the points in which the applications are consuming excessive energy and to examine how to reduce overall energy consumption by applications.

Hierarchical State Transition Matrix (HSTM) is a table-based modeling language for developing designs of software systems. Although widely used and adopted by (particularly Japanese) software industry, there is still lack of mechanized formal verification supports for conducting rigorous and automatic analysis to improve reliability of HSTM designs. In this paper, we first present a formalization of HSTM designs as state transition systems. Consequentially, based on this formalization, we propose a symbolic encoding approach, through which correctness of a HSTM design with respect to LTL properties could be represented as Bounded Model Checking (BMC) problems that could be determined by Satisfiability Modulo Theories (SMT) solving. We have implemented our encoding approach in a tool called Garakabu2 with the state-of-the-art SMT solver CVC3 as its back-ended solver. Furthermore, in our preliminary experiments, a conceptually simple but steadily effective way of accelerating SMT solving for HSTM designs is investigated and reported.