No abstract available.

The CrossCheck technique is beginning to gain acceptance as an effective low-cost solution to the ASIC testability problem. The technique provides massive observability by embedding test circuitry into the ASIC device. This allows highly accurate defect modeling and simulation with less computational resources than conventional techniques. This paper describes CrossCheck test technology and present results on its application to real-life designs. All these designs are sequential in nature with multiple, gated and asynchronous clocks. Bridging, comprehensive (opens and shorts) as well as conventional stuck-at I/O fault coverage, and CPU time and memory requirements are presented.>

A brief description is given of the CrossCheck test technology which provides the fundamental basis for this work. The authors present a practical analysis of transistor-level defects which result in accurate defect models in comparison to conventional fault models. The embedded test technology and accurate defect models are combined to form a high-quality test environment which is used to implement a high-performance test generation system. The authors present results on five ISCAS sequential benchmark circuits and two real designs. These results indicate that, in the presence of the embedded test electronics, test generation and fault simulation are considerably faster and test quality is substantially improved.>