This article presents a 28/39 GHz dual-band multi-mode low-noise amplifier (LNA), supporting wideband, concurrent, and reconfigurable dual-band operation modes. The proposed LNA consists of a three-stage cascode amplifier topology. The first and second stage loads incorporate a multi-tap switchable inductor and a reconfigurable transformer-based dual-band network, respectively. The primary coil inductance of the switchable inductor can be tuned by controlling the voltage of the secondary coil switches. The proposed reconfigurable dual-band network, comprising a transformer-based high-orderLCnetwork, provides different frequency responses for wideband, concurrent and reconfigurable modes. To mitigate the losses introduced by the transformer and switch, a Colpitts-style negative resistance compensation network (NRCN) is utilized. Fabricated in a 40-nm CMOS process, the LNA achieves the following measured performance: in wideband mode, the peak gain is 19.6 dB with a 3-dB bandwidth of 24.5-42.9 GHz, 3.4 dB minimum noise figure (NF), -9.6 to -6.5 dBm output 1-dB compression point (OP1dB). In concurrent mode, the measured results show the peak gains of 24/23.2 dB, 3.2/3.6 dB minimum NF and -11.8 to -7.6/-6.9 to -5.5 dBm OP1dB with 3-dB bandwidths of 25-31.7/38.1-42.5 GHz. The measured peak gains are 23.5/22dB with 3.1/3.5 dB minimum NF, -8.4 to -6.9/-7.3 to -4.9 dBm OP1dB and 3-dB bandwidths of 25.6-33.8/35.3-43.5 GHz in reconfigurable mode. The LNA occupies a core area of 0.14 mm2and consumes 15.2 mW, 19 mW, and 15.2 mW in wideband, concurrent, and reconfigurable modes, respectively.

In this paper, a Class-F voltage-controlled oscillator (VCO) with low-phase-noise (PN) and ultra-low-power consumption is proposed by reactivating the common-mode (CM) coupling factor in a 1:2 transformer. Unlike conventional designs that exclusively consider the differential-mode (DM) coupling factor in 1:2 transformers, our proposed architecture effectively leverages the combined potential of DM and CM coupling factors in a single transformer. For DM operation, a novel design method is presented to efficiently guide the design of ultra-low-power VCOs. This method provides clear insights into how Class-F3resonator parameters influence the loop gain characteristics, establishing a quantitative framework for performance optimization. Regarding CM operation, the 1:2 transformer’s coupling mechanism is analyzed in detail for the first time. The analysis reveals that strategic layout optimization of the center tap can reactivate the CM coupling factor, effectively expanding the CM resonance to reduce PN. Furthermore, by incorporating a tightly coupled tertiary coil, a local oscillator signal with high spectral purity is realized. Fabricated in a 110-nm CMOS process, the proposed VCO achieves a 20.2% frequency tuning range (FTR) from 10.45 to 12.80 GHz, consuming 0.38-0.50 mW with 0.2-V power supply. The measured PN exhibits −107 and −130 dBc/Hz at 1 MHz and 10 MHz offset from a 12.80-GHz carrier, respectively, with corresponding excellent figures-of-merit (FoM) of 192 and 195 dBc/Hz, respectively.

The channel knowledge map (CKM) is regarded as a digital twin of the wireless channel and provides location-specific channel information for environment-aware wireless communications. The channel gain map (CGM) is a typical form of CKM that stores spatially indexed channel gains over a target area, enabling fast link scheduling, coverage planning, and beam selection. Existing CGM construction methods mainly rely on propagation modeling or data-driven spatial completion, which can be computationally expensive or may inadequately capture site-specific propagation characteristics, thereby limiting prediction accuracy. To address this issue, we propose a three-stage Transformer-based CGM construction framework for predicting channel gains at arbitrary locations. In the first stage, the city map is discretized into grids, and the channel gain values within each grid are normalized to facilitate continuous spatial prediction. In the second stage, a Transformer-based coarse CGM prediction method is proposed to extract environmental features from the city map and generate a coarse CGM. In the third stage, a lightweight refinement network is designed, which leverages a small number of sparse measurements to refine the coarse predictions. Simulation results demonstrate that the proposed method significantly outperforms the state-of-the-art approaches across all performance metrics. In particular, compared with the existing optimal scheme, the proposed method achieves 32.81% and 20.63% reductions in normalized mean square error (NMSE) and root mean square error (RMSE), respectively, while improving the structural similarity index (SSIM) and peak signal-to-noise ratio (PSNR) by 2.08% and 3.71%, respectively.

Hybrid reconfigurable intelligent surfaces (HRIS) can enable 6 G vehicle-to-everything (V2X) system to attain promising localization and communication performance due to its flexible beamforming feature. However, without jointly designing the HRIS control and system resource allocation scheme, the HRIS-V2X system can not adapt to the dynamic environment efficiently. In addition, the optimization of HRIS reflectivity and communication time slice are both non convex and nonlinear problems. In this paper, we propose an asynchronous time division multiplexing (ATDM) protocol for the HRIS-V2X system to meet integrated localization and communications requirements. We analyze the role of HRIS in signal transmission according to squared position error bound (SPEB) and achievable rate (AR). Then, we propose an adaptive block coordinate descent (ABCD) algorithm to optimize the localization accuracy and channel transmission capability, which includes two parts: the time optimization and the reflectivity optimization. Time optimization employs the iterative projection method to find the optimal time slice scheme satisfying AR constraints. Reflectivity optimization uses the Adagrad method with an adaptive learning rate to gradually achieve the optimal reflectivity scheme. The simulation results indicate that our proposed ABCD algorithm has achieved a maximum 94.1% reduction in SPEB compared to greedy algorithm, genetic algorithm (GA), artificial rabbits optimization (ARO) and particle swarm optimization (PSO).

A high-speed multimodulus divider (MMD) is proposed in a 65-nm CMOS process. A 7-bit programmable counter (PC) featuring an innovative end-of-count (EOC) architecture and high-speed reset configuration is proposed for MMD applications. The proposed PC achieves an operating frequency of 11.7 GHz, which is 64.8% higher than the previously reported state-of-the-art design. In addition, an innovative analogous digital-standard-cell (A-STD) layout methodology is introduced to optimize parasitic capacitance and chip area in MMD implementation. By utilizing the above techniques along with a 20.5 GHz high-speed true-single-phase-clock (TSPC) dual-modulus prescaler (DMP), the MMD achieves a division-ratio range from 40 to 323, with a maximum frequency of 12.6 GHz at 1.2-V supply, consuming a total power of 3.07 mW. And by using the A-STD layout methodology, the MMD occupies a small chip area. The chip area of MMD is$56 \times 36 {\,}\boldsymbol {\mu }\text {m}^{2}$, which is less than 20% of that of prior works with similar functionality.

In this paper, a reconfigurable intelligent surface (RIS)-assisted millimeter-wave (mmWave) communication system with hybrid beamforming is considered, where the base station (BS) transmits signals to users via the RIS. Due to the difficulty in acquiring accurate channel state information (CSI) and the high complexity of hybrid beamforming design, a codebook-based method is employed to balance communication performance and computational cost. However, conventional codebook construction typically neglects the influence of surrounding communication environments, resulting in poor adaptability in complex mmWave scenarios. Therefore, we propose a three-stage environment-aware codebook design framework based on channel knowledge map (CKM) to enhance the adaptability of systems under different channel conditions. Specifically, in the first stage, a deep learning (DL)-based method is proposed to construct the CKM, which is a site-specific database that provides accurate CSI for given locations. In the second stage, the CSI of potential users is rapidly acquired based on the CKM, then a deep reinforcement learning (DRL) algorithm is employed to generate environment-aware codebooks by solving a sum achievable rate maximization problem. In the third stage, the end-to-end composite channel is first estimated. Then, the digital beamforming is computed by using the minimum mean square error (MMSE) criterion. Finally, the optimal analog beamforming and RIS phase shifts are selected through codebook scanning. Simulation results demonstrate that the proposed CKM-based environment-aware codebooks significantly outperform other codebook schemes in terms of sum achievable rate.

Electromagnetic structure (EMS) design plays a critical role in developing advanced antennas and materials, but remains challenging due to high-dimensional design spaces and expensive evaluations. While existing methods commonly employ high-quality predictors or generators to alleviate evaluations, they are often data-intensive and struggle with real-world scale and budget constraints. To address this, we propose a novel method called Progressive Quadtree-based Search (PQS). Rather than exhaustively exploring the high-dimensional space, PQS converts the conventional image-like layout into a quadtree-based hierarchical representation, enabling a progressive search from global patterns to local details. Furthermore, to lessen reliance on highly accurate predictors, we introduce a consistency-driven sample selection mechanism. This mechanism quantifies the reliability of predictions, balancing exploitation and exploration when selecting candidate designs. We evaluate PQS on two real-world engineering tasks, i.e., Dual-layer Frequency Selective Surface and High-gain Antenna. Experimental results show that our method can achieve satisfactory designs under limited computational budgets, outperforming baseline methods. In particular, compared to generative approaches, it cuts evaluation costs by 75$\tilde$85%, effectively saving 20.27$\tilde$38.80 days of product designing cycle.

In this paper, we revisit the problem of fair allocation with subsidy. We first consider the allocation of m indivisible chores to n agents with additive (dis)utility functions. Under the assumption that the maximum (dis)utility of an item can be compensated by one dollar, Wu et al. (WINE 2023) showed that a total of n/4 dollars suffices to guarantee a proportional allocation by rounding fractional allocations. Their subsidy guarantee is optimal when n is even. For odd n, there is still a small gap between the upper and lower bounds for the total subsidy. In this paper, we propose a much simpler algorithm for the problem, which does not require rounding fractional allocations, and achieves an optimal subsidy guarantee for all values of n. Different from existing works, our algorithm does not require the computation and rounding of fractional allocations and admits a much simpler analysis. We further show that our algorithm and analysis framework can be extended to the mixture of (subjective) goods and chores, achieving the optimal subsidy guarantee.

We consider the problem of fair allocation of m indivisible items to a group of n agents with subsidies (money). We address scenarios where agents have general additive cost/utility functions. Our work primarily focuses on the special case of three agents. Assuming that the maximum cost/utility of an item to an agent can be compensated by one dollar, we demonstrate that a total subsidy of 1/6 dollars is sufficient to ensure the existence of Maximin Share (MMS) allocations for both goods and chores. Additionally, we provide examples to establish the lower bounds of the required subsidies.

We investigate the closest distribution refinements problem, which involves a vertex-weighted bipartite graph as input, where the vertex weights on each side sum to 1 and represent a probability distribution. A refinement of one side’s distribution is an edge distribution that corresponds to distributing the weight of each vertex from that side to its incident edges. The objective is to identify a pair of distribution refinements for both sides of the bipartite graph such that the two edge distributions are as close as possible with respect to a specific divergence notion. This problem is a generalization of transportation, in which the special case occurs when the two closest distributions are identical. The problem has recently emerged in the context of composing differentially oblivious mechanisms. Our main result demonstrates that a universal refinement pair exists, which is simultaneously closest under all divergence notions that satisfy the data processing inequality. Since differential obliviousness can be examined using various divergence notions, such a universally closest refinement pair offers a powerful tool in relation to such applications. We discover that this pair can be achieved via locally verifiable optimality conditions. Specifically, we observe that it is equivalent to the following problems, which have been traditionally studied in distinct research communities: (1) hypergraph density decomposition, and (2) symmetric Fisher Market equilibrium. We adopt a symmetric perspective of hypergraph density decomposition, in which hyperedges and nodes play equivalent roles. This symmetric decomposition serves as a tool for deriving precise characterizations of optimal solutions for other problems and enables the application of algorithms from one problem to another. This connection allows existing algorithms for computing or approximating the Fisher market equilibrium to be adapted for all the aforementioned problems. For example, this approach allows the well-known iterative proportional response process to provide approximations for the corresponding problems with multiplicative error in distributed settings, whereas previously, only absolute error had been achieved in these contexts. Our study contributes to the understanding of various problems within a unified framework, which may serve as a foundation for connecting other problems in the future.

Graphs are crucial for modeling complex relationships in fields like social networks and biology. A key aspect in graph theory is identifying dense subgraphs, with applications in various domains. Density decomposition refines this by analyzing a graph's global density structure. This concept has been independently rediscovered in research areas like graph mining, algorithm design, and economics. Recent advancements in maximum-flow algorithms allow for nearly-linear time computation of the density vector, but they struggle with large real-world graphs. To address this, iterative first-order methods based on convex optimization, such as the Frank-Wolfe algorithm and momentum-based methods like accelerated FISTA, have been developed to approximate density vectors. This work explores density decomposition through market dynamics, where edges represent buyers and nodes represent sellers in a Fisher market model. The iterative proportional response process, which converges to the Fisher market equilibrium, provides an alternative interpretation of density decomposition. In each step, agents allocate resources based on the proportion of benefit received, moving the system toward equilibrium. Since each proportional response update can be seen as a gradient descent step, we investigate whether momentum methods can speed up convergence. Traditional momentum uses a linear combination of current and previous solutions, whereas our novel exponential momentum variant uses geometric interpolation, aligning better with proportional adjustments. Empirical evaluations on large-scale real-world and synthetic graphs confirm the effectiveness of our methods. Notably, the proportional response algorithm with exponential momentum outperforms existing methods, delivering improvements by several orders of magnitude in some cases. This advancement is significant, as the resulting density vector is crucial for many downstream tasks in graph mining and algorithm design.

A novel design approach is presented to extend the bandwidth and output power back-off (OBO) range of symmetric Doherty power amplifier. The traditional single variable regulation techniques are effective for output power back-off range extension only at single frequency points. Firstly, one phase dispersion (PD factor) is introduced to characterize the OBO range versus frequency. Secondly, multi-parameters optimization of PD factor, complex combining load (CCL), and out-phased current combining (OCC) is used to alleviate the conflict of bandwidth and OBO range. Dynamically optimizing frequencydependent CCL and OCC parameters to counteract the dispersion effect of the matching network thus enable the wideband OBO extension and expanding design flexibility of symmetric DPA. For demonstration, a symmetric DPA with 9dB OBO range is proposed with a fractional operation bandwidth of 36% within 1.8-2.6 GHz. Under the continuous-wave excitation, the fabricated DPA features a 9-dB output back-off (OBO) efficiency of 37.9%– 55% and a saturated efficiency of 55.7%–66.9%, respectively. When driven by a 20-MHz long-term evolution (LTE) modulated signal with 9-dB peak-to-average ratio (PAPR), the adjacent channel power ratio (ACPR) of the fabricated DPA is better than -50.1 dBc after digital predistortion.

This paper proposes a millimeter-wave (mmW) oscillator with “$2+1$” cores and triple operation modes to realize an octave-tuning range. An auxiliary core, comprising a switch and a negative transconductance cell, is introduced to the regular dual-core oscillator to generate a third mode with enhanced effective Q. This auxiliary core not only broadens the tuning range without compromising phase noise or chip area but also avoids the risk of introducing mismatch into two regular cores like triple-core oscillators. The demand for low interconnect resistance is relieved because of the merits of less core mismatch and extra magnetic injection lock path. The behavior of the proposed oscillator in different modes is studied analytically. A quantitative analysis of phase noise and interconnect resistance in the dual-core oscillator is presented and verified against circuit simulations. Implemented in a 65-nm CMOS process, the oscillator achieves a 72.24% tuning range from 16.35 to 35.48 GHz and a peak figure-of-merit of tuning range and area (FoM$_{\mathrm {TA}}$) of -217.07 dBc/Hz at 20.27 GHz with 1 MHz frequency offset. The chip operates from a 1 V supply with a power consumption from 6.3 to 21.76 mW and a core area of 0.075 mm2.

This paper presents a 6-bit bidirectional variable-gain vector-summing active phase shifter (BVG-AVSPS) in TSMC 65nm CMOS technology. The proposed BVG-AVSPS consists of a novel bidirectional quadrature generator, four dual-function bidirectional amplifiers and two input/output matching networks. The proposed hybrid-based quadrature generator achieves low orthogonal amplitude and phase mismatches over a wideband with bidirectionality. Dual-function bidirectional amplifiers are employed to achieve either vector modulation or gain control functions in different operational directions. To improve the phase shifting accuracy during gain tuning, compensation transistors are employed in the dual-function bidirectional amplifiers to minimize additional phase variation. The proposed input/output networks based on L-type coupled inductors ensure proper impedance matching for both input and output in TX and RX modes. For both TX and RX modes over 24 GHz~32 GHz, the measured RMS phase and gain errors are 1.25∘~2.4∘and 0.42 dB~0.56 dB throughout 12.3 dB gain tuning range, respectively. With the help of the compensation transistors, measured phase variation is less than ±2.1∘during output gain tuning. The core area of proposed BVG-AVSPS is 625 µm×355 µm.

This paper presents a compact PIN-diode-based single-pole double-throw (SPDT) switch for wideband RF systems. The series-shunt topology is adopted for the proposed switch. Compensating inductors are introduced to parallelly resonate with the off-capacitance of series diodes, creating an isolation peak. A two-pole highpass matching network is realized by introducing an additional inductor and reusing existing DC components, which ensures compact size and wideband capability. Moreover, the matching network enables independent control of ON-state operating band over the OFF-state, allowing optimized insertion loss and isolation at the desired center frequency. To assist analytical design, closed-form equations of the highpass matching network are derived through equivalent circuit analysis. For demonstration, one SPDT switch utilizing commercial PIN diodes and lumped RLC components is designed, fabricated, and measured. The measured results exhibit superior return loss of better than 20dB across 1.02-3.36 GHz attributed to the two-pole response. The insertion loss remains below 0.81 dB, reaching 0.457 dB at 2.6 GHz, while isolation is better than 27 dB, with a maximum of 71.8 dB at 2.25 GHz. Importantly, the proposed design can be scaled to mm-wave bands with better performances than their widely developed lowpass counterpart.

In this paper, a reconfigurable intelligent surface (RIS) is utilized to assist wireless-powered communication network (WPCN) for achieving integrated sensing and communication (ISAC). In this system, the ISAC base station (BS) first performs radar sensing for multiple targets and wireless power transfer (WPT) for multiple energy-constrained devices with assistance of RIS during the downlink (DL), then all devices transmit their data to the ISAC BS in the uplink (UL) by employing non-orthogonal multiple access (NOMA) with the use of harvested energy. To maximize the sum achievable throughput subject to the quality of service (QoS) constraints of communication devices and sensing quality constraint of targets, we jointly optimize the energy beamforming matrix, radar beamforming matrix, phase shift matrix of RIS, and transmission timeslot allocation in the DL and UL durations. To tackle this non-convexity problem, a two-stage solution is proposed. In the first stage, the energy and radar beamforming matrices, and phase shift matrix of RIS in the DL can be derived according to the penalty-based successive convex approximation (SCA) algorithm and Riemannian conjugate gradient (RCG) algorithm, respectively. In the second stage, the transmission timeslot allocation and phase shift matrix of RIS in the UL are obtained via the polar point method and penalty-based RCG algorithm, respectively. The final optimal results of each stage are yielded based on alternating optimization (AO) algorithm. Numerical results verify the significant improvement of deploying RIS for WPT and data transmission, and the superiority of the proposed optimization solution in improving the sensing performance and achievable throughput compared to other schemes.

While single reconfigurable intelligent surface (RIS)- aided systems have demonstrated potential in improving transmission performance, their ability to serve multi-user scenarios is inherently limited. In this paper, we investigate the deployment of multiple RISs to assist downlink (DL) millimeter-wave (mmWave) non-orthogonal multiple access (NOMA) communications between a base station (BS) and multiple users. For maximizing the system achievable throughput, we propose a two-stage resource allocation scheme. In the first stage, a two-step RIS-user pairing scheme is proposed by combining the Gale-Shapley (GS) algorithm and the worst connection swapping (WCS) algorithm. In the second stage, based on the pairing results from the first stage, an alternating optimization (AO) algorithm is utilized to iteratively optimize RIS phase shifts, digital precoder, and power allocation. During each iteration, with fixed digital precoder and arbitrary feasible power allocation, the optimal RIS phase shifts can be obtained by the difference of convex (D. C.) programming and semidefinite relaxation (SDR) techniques. Then, the minimum mean-squared error (MMSE)-based digital precoder is adopted. Based on the derived RIS phase shifts and digital precoder, the optimized power allocation can be derived by reusing the D. C. programming subject to the constraint of decoding rate for successive interference cancellation (SIC). Simulation results show that the proposed pairing scheme can achieve near-optimal system achievable throughput, while significantly reducing the computational complexity. In addition, the proposed two-stage resource allocation scheme also demonstrates advantages in improving the overall achievable throughput of the system.

In this paper, a reconfigurable intelligent surface(RIS)-assisted millimeter-wave (mmWave) non-orthogonal multiple access (NOMA) communication system is considered, where the RIS is virtually partitioned into several sub-RISs to serve different user clusters. We aim to maximize the sum achievable rate of the considered system by jointly optimizing user clustering, RIS partitioning, active beamforming, passive beamforming, and power allocation, subject to the quality-of-service (QoS) requirements of each user and the maximum transmit power constraint of the base station (BS). To tackle the formulated non-convex joint optimization problem, a three-stage algorithm based on machine learning (ML) is proposed. In the first stage, user clustering is performed by combining the K-means algorithm and the Gaussian mixture model (GMM). In the second stage, a deep learning (DL)-based RIS partitioning method is proposed, which utilizes double cascaded deep neural networks (DNNs) to partition the RIS into multiple sub-RISs virtually, each of which serves a user cluster. In the third stage, a deep reinforcement learning (DRL) algorithm based on deep deterministic policy gradient (DDPG) is invoked to obtain the active beamforming, passive beamforming, and power allocation. Simulation results demonstrate that the proposed RIS partitioning method can effectively improve the utilization of RIS and thereby increase the total throughput of the system. Moreover, the sum achievable rate obtained by the proposed ML-based three-stage algorithm is higher than that of the conventional alternating optimization (AO) algorithm.

We study the problems of computing the Voronoi diagram and a triangulation of a set of n 2 points with O ( log ⁡ n ) -bit coordinates in the Euclidean plane in a substantially sublinear in n number of rounds in the congested clique model with n nodes. First, we observe that if the points are uniformly at random distributed in a unit square then their Voronoi diagram within the square can be computed in O ( 1 ) rounds with high probability (w.h.p.). Next, we show that if a very weak smoothness condition is satisfied by an input set of n 2 points with O ( log ⁡ n ) -bit coordinates in the unit square then the Voronoi diagram of the point set within the unit square can be deterministically computed in O ( log ⁡ n ) rounds in this model. Finally, we present a deterministic O ( log ⁡ n ) -round protocol for a triangulation of n 2 points with O ( log ⁡ n ) -bit coordinates in the Euclidean plane. It relies on our novel method for extending triangulations of two planar point sets separated by a straight line to a complete triangulation of the union of the sets in O ( 1 ) rounds.

A multiband reconfigurable all-digital transmitter (ADT) employing a sturdy multistage noise-shaping (SMASH) delta-sigma modulation (DSM) is proposed in this article. TheN-stage SMASH DSM is presented digitally using unit signal transfer functions across cascaded stages, which supports arbitrary-stage extension for multiband transmission. Each stage is associated with a specific passband. By activating different stage numbers and adjusting only two parameters per stage, the numbers and frequencies of passbands are reconfigured simply and independently. Consequently, computational resources are significantly reduced, which is especially beneficial for four or more bands. Furthermore, the DSM outputs are directly extracted from individual stages to simplify the ADT architecture while the high efficiencies of subsequent power amplifiers (PAs) are maintained. By using the SMASH DSM, an ADT with multiband reconfigurable characteristics is proposed. With a resource-performance tradeoff, an ADT prototype based on a 2–2 SMASH DSM is implemented on a field programmable gate array (FPGA), which uses only 256 DSP48 slices. The transmissions are switched between single-band and dual-band configurations with carrier frequencies (CFs) independently tunable over 0–3.2 GHz. Measured adjacent channel leakage ratios (ACLRs) for 10- and 20-MHz dual-band signals are below −45 and −39.5 dBc, respectively, with error vector magnitudes (EVMs) below 1.6%. These results verify the agile multiband reconfiguration and excellent performance of the proposed SMASH DSM-based ADT.

In this paper, a reconfigurable intelligent surface (RIS)-assisted millimeter-wave (mmWave) multi-hop communication system is considered, where the base station (BS) transmits signals to remote users via multi-hop paths formed by multiple RISs. We aim to maximize the sum achievable rate by jointly optimizing multi-hop path scheduling, active beamforming, and passive beamforming, while satisfying the maximum transmit power of the BS. To tackle the formulated non-convex joint optimization problem, a machine learning (ML)-based two-stage algorithm is proposed. In the first stage, a multi-hop path scheduling algorithm based on graph neural networks (GNN) is investigated. Specifically, the considered system is first modeled as a graph topology, where the BS, RIS, and users are all served as nodes. Then, the weights between adjacent nodes associated with the path gain and the number of RIS reflection units are defined based on the expressions of RIS-assisted equivalent channels. Finally, a GNN-based multi-hop path scheduling algorithm is proposed. In the second stage, according to the obtained optimal multi-hop path, the deep deterministic policy gradient (DDPG) strategy is adopted to optimize the active beamforming of the BS and the passive beamforming of the selected RISs. Simulation results demonstrate that the proposed GNN-based multi-hop path scheduling algorithm maintains an error within 3% compared to the global optimal solution and outperforms the graph-based methods. Additionally, the proposed two-stage algorithm improves the sum achievable rate by approximately 27.6% compared to the alternating optimization (AO) algorithm.

This article presents a CMOS voltage-combined Doherty power amplifier (PA) based on a broadband compact load modulation network (LMN) for fifth-generation (5G) millimeter-wave (mm-wave) mobile communication applications. By analyzing the frequency response of different types of Doherty power combiner, a novel voltage-combined Doherty LMN with shorted TL and corresponding design procedure are proposed to achieve broadband power back-off (PBO) bandwidth and compact footprint. A compact quadrature hybrid coupler without lumped capacitor is also devised to generate wideband quadrature signals. To improve PBO efficiency, an envelope detector is adopted to produce adaptive DC bias for auxiliary path. For the proof of concept, a dual-driver Doherty PA is implemented in 65-nm bulk CMOS technology with a chip size of 0.42 mm2 including all pads. The PA achieves a 3-dB small-signal$S_{21}$bandwidth from 21.1 to 30.4 GHz and a 1-dB saturated output power ($P_{\text {sat}}$) bandwidth from 24 to 30 GHz. The measured$P_{\text {sat}}$, output 1-dB compression point ($OP_{\text {1dB}}$), peak power-added efficiency (PAE) and PAE at 6dB-PBO are 20.0 dBm, 19.1 dBm, 24.6% and 20.0% at 27 GHz, respectively. For modulation measurements, the proposed PA under 64-quadrature-amplitude-modulated (64-QAM) signal at a data rate of 0.6/2.4 Gb/s achieves average output power ($P_{\text {avg}}$) of 11.5/4.8 dBm and average drain efficiency of 14.1%/3.9% with −25/−24.5 dB of error vector magnitude (EVM) and −29/−25.6 dBc of adjacent channel leakage ratio (ACLR) at 28 GHz, respectively.

The article proposes a modified series compensation (MSC) outphasing power amplifier (OPA) that maximizes saturation output power and extends power back-off range. The proposed OPA enables achieving output power back-off (OBO) compensation without affecting the saturation matching. Then, the circuit structure is simplified by introducing a post-matching circuit to integrate the combiner and the reactive compensation network (RCN). Moreover, a simplified dual-impedance matching network (DIMN) is placed between each transistor and the output combiner, leading to increased OBO range with improved efficiency. This technique not only takes into consideration the influence of parasitic parameters but also match the required impedance at both saturation and OBO points, simultaneously. The above design idea is successfully verified by using the gallium nitride (GaN) high-electron-mobility transistor (HEMT) to develop an OPA circuit operating at 2.6 GHz, providing 45.2 dBm of peak output power. At the 12-dB output back-off point, the drain efficiency reaches 61.5%. In addition, the prototype achieves values of the adjacent channel leakage ratio (ACLR) equal to -48.17 dBc and 47.74 dBc for LTE modulated signal with 8 dB PAPR value and for 5G NR signal with 11.7 dB PAPR value, respectively.

Sparse matrix-vector multiplication (SpMV) is crucial in many scientific and engineering applications, particularly concerning the effectiveness of different sparse matrix storage formats for various architectures, no single format excels across all hardware. Previous research has focused on trying different algorithms to build predictors for the best format, yet it overlooked how to address the issue of the best format changing in the same hardware environment and how to reduce prediction overhead rather than merely considering the overhead in building predictors. This paper proposes a novel classification algorithm for optimizing sparse matrix storage formats, DyLaClass, based on dynamic labeling and flexible feature selection. Particularly, we introduce mixed labels and features with strong correlations, allowing us to achieve ultra-high prediction accuracy with minimal feature inputs, significantly reducing feature extraction overhead. For the first time, we propose the concept of the most suitable storage format rather than the best storage format, which can stably predict changes in the best format for the same matrix across multiple SpMV executions. We further demonstrate the proposed method on the University of Florida’s public sparse matrix collection dataset. Experimental results show that compared to existing work, our method achieves up to 91% classification accuracy. Using two different hardware platforms for verification, the proposed method outperforms existing methods by 1.26 to 1.43 times. Most importantly, the stability of the proposed prediction model is 25.5% higher than previous methods, greatly increasing the feasibility of the model in practical field applications.

Charging scheduling plays a crucial role in ensuring durable operation for wireless rechargeable sensor networks. However, previous methods cannot meet the strict requirements of a high node survival rate and high energy usage effectiveness. In this article, we propose a multi-type charging scheduling strategy to meet such demands. In this strategy, the network is divided into an inner ring and an outer ring to satisfy different demands in different areas. The inner ring forms a flat topology, and adopts a periodic and single-node charging pattern mainly for a high node survival rate. A space priority and a time priority are designed to determine the charging sequence of the nodes. The optimal charging cycle and the optimal charging time are achieved by mathematical derivations. The outer ring forms a cluster topology, and adopts an on-demand and multi-node charging pattern mainly for high energy usage effectiveness. A space balancing principle and a time balancing principle are designed to determine the charging positions of the clusters. A gravitational search algorithm is designed to determine the charging sequence of the clusters. Several simulations verify the advantages of the proposed solution in terms of energy usage effectiveness, charging failure rate, and average task delay.

Abstract We consider a graph orientation problem that can be viewed as a generalization of Minimum Graph Coloring. Our problem takes as input an undirected graph $$G = (V, E)$$ G = ( V , E ) in which every edge $$\{u, v\} \in E$$ { u , v } ∈ E has two (potentially different and not necessarily positive) weights representing the lengths of its two possible directions ( u , v ) and ( v , u ), and asks for an orientation, i.e., an assignment of a direction to each edge of G , such that the length of a longest simple directed path in the resulting directed graph is minimized. A longest path in a graph is not always a maximal path when some edges have negative lengths, so the problem has two variants depending on whether all simple directed paths or maximal simple directed paths only are taken into account in the definition. We prove that the problems are NP-hard to approximate even if restricted to subcubic planar graphs, and develop fast polynomial-time algorithms for both problem variants for three classes of graphs: path graphs, cycle graphs, and star graphs.

This paper presents compact 24–35 GHz filtering low noise amplifier (LNA) and filtering switch in 28-nm CMOS technology. A compact mixed magnetic-electric coupling circuit is designed, where a transmission zero is introduced out of the passband due to the cancellation of the magnetic and electric couplings. By analyzing the impedance characteristics, this structure can be designed with the impedance conversion function to replace the widely used transformers in integrated circuit designs. It shows the advantages of easy control of coupling coefficient and out-of-band rejection. Then, an LNA employing the magnetic-electric coupling circuits as impedance matching networks is designed. Image rejection can be achieved without increasing the circuit area. Moreover, by loading transistors to this mixed magnetic-electric coupling circuit, the input impedance can be controlled by the parasitic components of the transistor. Subsequently, a filter passband can be switched on and off, realizing a very compact filtering single-pole single-throw (SPST) switch. The fabricated filtering LNA is measured with a 3-dB bandwidth of 24–35 GHz, a noise figure (NF) of 2.4-3.6 dB, a maximum gain of 22 dB, and suppression of better than 25 dBc below 18 GHz. The filtering switch shows a minimum on-state loss of 2.1 dB at 28.6 GHz with better than 12.9 dB rejection below 16 GHz and off-state isolation of higher than 19 dB.

This paper presents an optimization method of wideband filtering power amplifier (PA) with high efficiency. In order to achieve the expected high efficiency in the wide passband and reduce design difficulty, a high-performance area-based impedance target for computer-aided automatic optimization is proposed, which avoids the unexpected efficiency degradation caused by the conventional impedance target. In the meanwhile, the out-of-band optimization target described by impedance is also proposed to obtain bandpass filtering characteristic. The in-band and out-of-band optimization targets are utilized to design the output matching network to realize fundamental and harmonic impedance matching precisely, as well as the filtering response. For demonstration, a filtering PA operating in 3.3-3.8 GHz is implemented and measured. The measured small-signal$S$-parameter exhibits flat gain in passband and good bandpass filtering response. The measured power-added efficiency (PAE) is larger than 62% within the entire working band and the highest PAE is 71.7%.

A design strategy to enhance the efficiency of the dual-mode Doherty power amplifier (DPA) is proposed. The continuous multiple harmonic regulation approach is adopted to realize high efficiency of dual-mode DPA in a wide operating frequency band. Multi-harmonic control and dual-mode impedance matching are performed by a single load modulation network. The DPA’s operating frequency band and harmonic control type can be simultaneously switched through reciprocal gate bias. A DPA using GaN devices with continuousClass$F$for Mode I (1.5–2.4 GHz) andClass$J$/continuous inverseClass$F$for Mode II (1.3–1.4 GHz/2.5–2.7 GHz) is designed and implemented. The fabricated DPA achieves a measured 10.5–14.3-dB gain and 39.2–41.8-dBm saturated power. Due to the proposed strategies, 39.1%–58.2% and 55.6%-71.9% drain efficiencies are obtained respectively at 6-dB output power back-off and saturation output power for the designed DPA. For the down-link long-term evolution (LTE) signal with a channel bandwidth of 20 MHz and a peak-to-average power ratio (PAPR) of 7.5 dB, the average adjacent channel power ratio of the fabricated DPA is better than 40 dBc after digital predistortion at 1.3, 2.0 and 2.6 GHz with average output power back-off (OBO) efficiency of 37.8%, 39.3% and 43.3%.

This paper presents a high-flexibility and low-cost transceiver (TRX) in 65-nm CMOS process for fifth-generation (5G) communications. The TRX is based on local-oscillator (LO) phase-shifting architecture with 5 bits of gain control and 6 bits of phase control. To enhance the transceiver gain, bandwidth, efficiency, noise performance, and achieve ultra-low amplitude and phase errors without any calibration, a variety of innovative techniques are introduced in this work. The TX path demonstrates a measured peak conversion gain (CG) of 43.1 dB with the IF fractional bandwidth of 79% from 3.5 to 8.1 GHz and the RF of20% from 23.4 to 28.5 GHz. The measured TX OP1dB is up to 13.3 dBm at26 GHz. In the RX mode, the measured peak CG is 29.6 dB with 134% fractional bandwidth of the IF (2.1 to 10.6 GHz), 19% of the RF (23.7 to 28.6 GHz) and the minimum noise Figure is 5.5 dB (including T/R switch). Moreover, the TRX with 6-bit phase resolution realizes a measured RMS amplitude and phase errors of less than 0.63 dB and 2. 4°, respectively. The proposed wideband transceiver simultaneously implements broadband RF/LO/IF while maintaining ultra-low gain and phase errors without any calibration. Such a system with only one chip can meet the requirements of IF, LO and RE frequency combinations of different scenarios, which is suitable for high data-rate and low cost 5G applications.

In this paper, two types of balanced-to-unbalanced quadrature couplers with six hybrid ports and arbitrary power division ratio are proposed. For Type 1, the quadrature coupler can realize two power division functions, including balanced/unbalanced to balanced-unbalanced-hybrid, and for Type 2, the quadrature coupler contains balanced -to-unbalanced and unbalanced-to-balanced power division functions. To reduce the circuit size, double-sided parallel-strip line (DSPSL) swap structure is used to replace the half-wavelength transmission line, and compact circuit size can be easily achieved. To validate the performance of the quadrature couplers, two types of the balanced-to-unbalanced quadrature couplers centered at 1 GHz with power division ratios 1:1 and 3:1 are fabricated and measured, respectively. The common mode suppression higher than 10 dB (bandwidths over than 176%) can be realized, the isolation and in-band matching level can be also improved.

An odd-element half-wave-rectification superposition (OHS) technique is presented and verified for designing the high-multiplication factor frequency multipliers. The proposed OHS technique superposes N odd-element phase-shifted half-wave-rectification (HWR) fundamental signals ($f_{0}$) to extract the 2N-order harmonic (2N$f_{0}$) while canceling the fundamental ($f_{0}$) and the 2ndto (2N-1)th harmonics without extra filtering. Compared with the reported even-element half-wave-rectification superposition technique (EHS) technique, the proposed OHS technique can realize the same multiplication factor but requires only a half number of the input HWR signals. Thus, the proposed OHS technique can be applied to design the high-multiplication factor frequency multiplier that is difficult to be implemented using the reported EHS technique. To verify the validity of the proposed OHS technique, a differential$\times 6$frequency multiplier with the input frequency range of 5-7GHz and output frequency range of 30–42 GHz was implemented in 65 nm CMOS process. The experimental results indicate that the implemented$\times 6$frequency multiplier exhibits more than 23 dBc rejection to the fundamental and 2ndto 5thharmonics without the extra filter. The DC power consumption is 4.6 mW for the core circuit.

An simplified vector-sum phase shifter (VSPS) topology is proposed in this article. The proposed VSPS topology employs only one 90° coupler to perform as both an I/Q generator and a vector summer. Compared with the literaturally reported VSPS, the proposed VSPS features a simpler topology and improved noise figure (NF) performance. Moreover, active baluns based on the self-calibration technique are employed to provide antiphase signals and improve the gain performance of the VSPS. For demonstration, a 24–30-GHz VSPS based on the proposed topology is implemented in the 65-nm CMOS process, exhibiting 3.5° rms phase error and 0.9-dB rms gain error. The average gain of the implemented VSPS is as high as 9 dB at the central frequency of 27 GHz. The NF ranges from 4.8 to 9 dB from 24 to 30 GHz, and the core chip size is$0.36\times0.59$mm2.

A 9.8–30.1 GHz CMOS low-noise amplifier (LNA) with a 3.2-dB minimum noise figure (NF) is presented. At the architecture level, a topology based on common-gate (CG) cascading with a common-source (CS) amplifier is proposed for simultaneous wideband input matching and relatively high gain. At the circuit level, multiple techniques are proposed to improve LNA performance. First, in the CG stage, loading effect is properly used instead of the conventional feedback technique, to enable simultaneous impedance and noise matching. Second, based on in-depth theoretical analysis, the inductor- and transformer-based g m -boosting techniques are employed for the CG and CS stages, respectively, to enhance the gain and reduce power consumption. Third, the floating-body method, which was originally proposed to lower NF in CS amplifiers, is adopted in the CG stage to further reduce NF. Fabricated in a 65-nm CMOS technology, the LNA chip occupies an area of only 0.2 mm 2 and measures a maximum power gain of 10.9 dB with −3 dB bandwidth from 9.8 to 30.1 GHz. The NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire bandwidth. The LNA consumes 15.6 mW from a 1.2-V supply.

In this paper, dual-mode oval dielectric resonator (DR) is proposed as common resonator to realize all four kinds of balanced and unbalanced duplexers. The conventional topology is replaced with the novel one of sharing input and output dual-mode resonators at the same time for miniaturization. By adjusting the aspect ratio and height of the oval DR, the two modes are separated properly to form two channels of duplexers. After locating probes delicately according to the orthogonality of dual-mode fields, the channel transmission and isolation are ensured simultaneously under sharing output DR. Moreover, both dual-mode unbalanced and balanced operations are studied to extend the topology to all four kinds of duplexers. For verification, balanced-to-unbalanced (B-U) and balanced-to-balanced (B-B) duplexers are both fabricated and tested. Low insertion losses better than 0.59 dB are achieved in both two designs. High isolations lower than -36 dB and -50 dB and common-mode rejections lower than -44 dB and -52 dB are observed in the B-U and B-B duplexers, respectively. The exhibited high performance with reduced resonators demonstrates the potentials of the proposed duplexers in miniaturized FDD communication systems for connecting balanced/unbalanced transceivers with balanced/unbalanced antennas.

In this work, an on-chip bandpass filter (BPF) with ultra-wideband, low insertion loss, sharp selectivity and excellent in-band flatness is achieved using a novel design approach based on a quasi-lumped-element method. This approach simply utilizes folded metal strip lines with metal-insulator-metal (MIM) capacitors. To understand the principle of the presented design approach, theoretical analysis is given by means of a simplified equivalent LC-circuit model. Using the analyzed results with a full-wave electromagnetic (EM) simulator to guide the design, a BPF is implemented and fabricated in a standard 0.13-μm (Bi)-CMOS technology. The measurements show that a return loss of better than 10 dB is obtained from 13.5 to 32 GHz. Furthermore, the insertion loss of less than 2.3 dB is achieved with less than 0.1 dB in-band magnitude ripple. The BPF size without measurement pads is only 0.148 mm2(0.37 × 0.4 mm2).

The objective of this paper is to provide the context, physical insight, and perspective on antennas in wireless communications. Although it does not mean to be comprehensive, the four key technologies related to small antenna designs to be reviewed and discussed, including multiband planar inverted-F antennas, broadband folded patch antennas, compact differentially fed antennas, and miniature circularly polarized patch antennas, would cover a wide range of topical interests and practical applications. A brief overview of computer software for analyzing these antennas is also provided. Hopefully, this paper will be beneficial for the diverse engineering readership of the IEEE.